AMD 8151 specifications Reserved

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

•Host-initiated transactions inside the windows are routed to the AGP bus.

•PCI transactions initiated on the AGP bus inside the windows are not claimed by the IC.

•Host initiated transactions outside the windows are passed through the tunnel or master aborted if the IC is at the end of a HyperTransport technology chain.

•PCI transactions initiated on the AGP bus outside the windows are claimed by the IC using medium decod-

ing and passed to the host.

So, for example, if IOBASE > IOLIM, then no host-initiated IO-space transactions are forwarded to the AGP bus and all AGP-bus-initiated IO-space (not configuration) transactions are forwarded to the host. If MEM- BASE > MEMLIM and PMEMBASE > PMEMLIM, then no host-initiated memory-space transactions are for- warded to the AGP bus and all AGP-bus-initiated memory-space (not configuration) transactions are forwarded to the host.

DevB:0x1C. Default: 0220 01F1h

Attribute: See below.

Bits

Description

 

 

 

 

31:30

Reserved.

 

 

 

29

RMA: received master abort. Read; set by hardware; write 1 to clear. 1=The IC received a master

 

abort as a PCI master on the AGP bus. Note: this bit is cleared by PWROK reset but not by RESET#.

 

 

28

RTA: received target abort. Read; set by hardware; write 1 to clear. 1=The IC received a target abort

 

as a PCI master on the AGP bus. Note: this bit is cleared by PWROK reset but not by RESET#.

 

 

27

STA: signaled target abort. Read; set by hardware; write 1 to clear. 1=The IC generated a target

 

abort as a PCI target on the AGP bus. The IC generates target aborts if it receives a target abort (a non-

 

NXA error) response from the host to an AGP bus PCI master transaction request. Note: this bit is

 

cleared by PWROK reset but not by RESET#.

 

 

 

26:16

Read only. These bits are fixed in their default state.

 

 

15:12

IOLIM. IO limit address bits[15:12]. See DevB:0x[30:1C] above.

 

 

 

11:8

Reserved.

 

 

 

7:4

IOBASE. IO base address bits[15:12]. See DevB:0x[30:1C] above.

 

 

 

3:0

Reserved.

 

 

 

 

DevB:0x20. Default: 0000 FFF0h

Attribute: Read-write.

Bits

Description

 

 

 

31:20

MEMLIM. Non-prefetchable memory limit address bits[31:20]. See DevB:0x[30:1C] above.

 

 

 

19:16

Reserved.

 

 

 

15:4

MEMBASE. Non-prefetchable memory base address bits[31:20]. See DevB:0x[30:1C] above.

 

 

 

3:0

Reserved.

 

 

 

 

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Contents Device Features OverviewCover AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents System block diagram Configuration space Ball designations Rev 3.03 July 12List of Tables IO signal types Tunnel Link Signals AGP Signals ACALD, S and ACALD, S#. Compensation pins forSERR# and PERR# signals are not supported on the AGP bridge Power Plane Sequencing Test and Miscellaneous SignalsPower and Ground Reset And Initialization Functional Operation OverviewClocking Clock GatingTunnel Links Link PHYAGP Tags, UnitIDs, And OrderingTranslation from AGP requests to link requests AGP transaction Link transactionVarious Behaviors AGP Compensation And Calibration CyclesConfiguration Space Registers Register OverviewRegister Naming and Description Conventions AGP Device AGP BridgeRegister attributes Configuration spacesMemory mapped address spaces AGP Device Status And Command Register DevA0x04 RESET#AGP Device Revision and Class Code Register DevA0x08 REVISION. Read onlyDefault 0000 0000h Attribute Read write once Default 0000 00A0h Attribute Read onlyAGP Device Subsystem ID and Subsystem Vendor ID Register AGP Capabilities PointerAGP Miscellaneous Control Register DevA0x40 Default 0000 0000h Attribute See below24888 Rev 3.03 July 12 Nctl Updated by the hardware approximately every 8 microseconds 1514Pctl 1Fh, then 1Fh is applied 11bAGP Revision and Capability Register AGP Status RegisterBit Gart support. This bit fixed low Host translation#. This bit fixed lowAGP Command Register Default 0000 0000h Attribute Read-writeRates Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardDefault 0001 0F00h Attribute See below AGP3MD DrateAGP Control Register AGP Aperture Size RegisterLink Command Register Garthi Gart base address register highGartlo Gart base address register low Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Enumeration Scratchpad Register DevA0xD4 Link Frequency Capability 0 Register DevA0xCCLink Frequency Capability 1 Register DevA0xD0 Bctl Default See below Attribute See belowBehavior 3021 Reserved 2016 Actl Sum exceeds 1Fh, then 1Fh is applied 11bClock Control Register Must be high. See .3.1 for detailsAGP Bridge Configuration Registers AGP Bridge Status And Command Register DevB0x04AGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x3C DevB0x24. Default 0000 FFF0h Attribute Read-writeDefault 0000 00FFh Attribute See below Absolute maximum ratings Operating rangesElectrical Data Absolute Ratings Operating RangesCurrent and power consumption DC characteristics for signals on the VDD33 power planeDC Characteristics Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 AC data for common clock operation of AGP signals AC CharacteristicsSymbol Parameter Description Min Max Units AC data for clocksAC data for clock-forwarded operation of AGP signals AGPBall Designations Top side viewSignal BGA positions Signal name BallPower and ground BGA positions Signal Ball NamePackage Specification Package mechanical drawingHigh Impedance Mode Nand Tree ModeTest modes TestNand tree 2 output signal is STRAPL4 Appendix Revision History Revision

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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