AMD 8151 specifications Actl, Sum exceeds 1Fh, then 1Fh is applied 11b, Clock Control Register

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24888 Rev 3.03 - July 12, 2004AMD-8151TMAGP Tunnel Data Sheet

6:5

ACTL: link side A PHY control value. Read-write. These two bits combine to specify the PHY

 

compensation value that is applied to side A of the tunnel as follows:

 

 

ACTL

Description

 

 

00b

Apply CALCCOMP directly as the compensation value.

 

 

01b

Apply ADATA directly as the compensation value.

 

 

10b

Apply the sum of CALCCOMP and ADATA as the compensation value. In

 

 

 

DevA:0x[E4, E0], if the sum exceeds 13h, then 13h is applied. In DevA:0x[E8], if the

 

 

sum exceeds 1Fh, then 1Fh is applied.

 

 

11b

Apply the difference of CALCCOMP minus ADATA as the compensation value. If the

 

 

difference is less than 01h, then 01h is applied.

 

 

The default value of this field (from PWROK reset) is controlled by the CMPOVR signal. If

 

CMPOVR = 0, the default is 00b. If CMPOVR = 1, the default is 01b.

 

 

 

4:0

ADATA: link side A data value. Read-write. This value is applied to the side A of the tunnel PHY

 

compensation as described in ACTL. The default for DevA:0x[E4, E0] is 08h. The default for

 

DevA:0xE8 is 0Fh.

 

 

 

 

Clock Control Register

DevA:0xF0

 

 

 

 

See section 4.3.1 for details on clock gating. AMD system recommendations for System Management Action Field (SMAF) codes are: 0=ACPI C2; 1=ACPI C3; 2=FID/VID change; 3=ACPI S1; 4=ACPI S3; 5=Throt- tling; 6=ACPI S4/S5. For server and desktop platforms, AMD recommends setting this register to 0004_0008h (to gate clocks during S1). For mobile platforms, AMD recommends setting this register to 0004_0A0Ah (to gate clocks during C3 and S1).

Default: 0000 0000h.

Attribute: Read-write.

Bits Description

31:19 Reserved.

18CGEN: clock gate enable. 1=Internal clock gating, as specified by bits[7:0] of this register, is enabled.

17Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.

16Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.

15:8

ECGSMAF: external clock gating system management action fields. Each of the bits of this field

 

correspond to SMAF values that are captured in Stop Grant cycles from the host. For each bit,

 

1=When LDTSTOP# is asserted prior to a Stop Grant cycle in which the SMAF field matches the

 

ECGSMAF bit that is asserted, then A_PCLK and internal clock grids associated with the AGP

 

bridges are forced low. 0=A_PCLK and the internal clock grids are active while LDTSTOP# is

 

asserted. For example, if A_PCLK gating is required for SMAF values of 3 and 5, then ECGSMAF[3,

 

5] must be high. See section 4.3.1 for details.

 

 

7:0

ICGSMAF: internal clock gating system management action fields. Each of the bits of this field

 

correspond to SMAF values that are captured in Stop Grant cycles from the host. For each bit,

 

1=When LDTSTOP# is asserted prior to a Stop Grant cycle in which the SMAF field matches the

 

ICGSMAF bit that is asserted, then the IC power is reduced through gating of internal clocks. 0=No

 

power reduction while LDTSTOP# is asserted. For example, if clock gating is required for SMAF

 

values of 3 and 5, then ICGSMAF[3, 5] must be high. See section 4.3.1 for details.

 

 

 

 

 

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Contents Overview Device FeaturesCover AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Power Plane Sequencing Test and Miscellaneous SignalsPower and Ground Functional Operation Overview Reset And InitializationClocking Clock GatingLink PHY Tunnel LinksAGP Tags, UnitIDs, And OrderingAGP transaction Link transaction Translation from AGP requests to link requestsVarious Behaviors AGP Compensation And Calibration CyclesRegisters Register Overview Configuration SpaceRegister Naming and Description Conventions AGP Device AGP BridgeRegister attributes Configuration spacesMemory mapped address spaces RESET# AGP Device Status And Command Register DevA0x04AGP Device Revision and Class Code Register DevA0x08 REVISION. Read onlyDefault 0000 00A0h Attribute Read only Default 0000 0000h Attribute Read write onceAGP Device Subsystem ID and Subsystem Vendor ID Register AGP Capabilities PointerAGP Miscellaneous Control Register DevA0x40 Default 0000 0000h Attribute See below24888 Rev 3.03 July 12 Nctl 1514 Updated by the hardware approximately every 8 microsecondsPctl 1Fh, then 1Fh is applied 11bAGP Status Register AGP Revision and Capability RegisterBit Gart support. This bit fixed low Host translation#. This bit fixed lowDefault 0000 0000h Attribute Read-write AGP Command RegisterRates Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardAGP3MD Drate Default 0001 0F00h Attribute See belowAGP Control Register AGP Aperture Size RegisterGarthi Gart base address register high Link Command RegisterGartlo Gart base address register low Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Enumeration Scratchpad Register DevA0xD4 Link Frequency Capability 0 Register DevA0xCCLink Frequency Capability 1 Register DevA0xD0 Bctl Default See below Attribute See belowBehavior 3021 Reserved 2016 Sum exceeds 1Fh, then 1Fh is applied 11b ActlClock Control Register Must be high. See .3.1 for detailsAGP Bridge Status And Command Register DevB0x04 AGP Bridge Configuration RegistersAGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x3C DevB0x24. Default 0000 FFF0h Attribute Read-writeDefault 0000 00FFh Attribute See below Operating ranges Absolute maximum ratingsElectrical Data Absolute Ratings Operating RangesDC characteristics for signals on the VDD33 power plane Current and power consumptionDC Characteristics Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 AC Characteristics AC data for common clock operation of AGP signalsSymbol Parameter Description Min Max Units AC data for clocksAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationNand Tree Mode High Impedance ModeTest modes TestNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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