AMD 8151 specifications Rev 3.03 July 12, AGP Miscellaneous Control Register DevA0x40

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24888

Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

AGP Miscellaneous Control Register

DevA:0x40

 

 

Default: 0000 0000h

Attribute: See below.

Bits

Description

 

 

 

 

31:8

Reserved.

 

7Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.

6 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. 5 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. 4 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.

3FWDIS: fast write disable. Read-write. 1=DevA:0xA4[FWSUP] is low. 0=DevA:0xA4[FWSUP] is high.

28XDIS: AGP 3.0 signaling mode disable. Read-write. 0=The IC drives A_MB8XDET# low to indicate support for AGP 3.0 signaling. 1=The IC does not drive A_MB8XDET low. This bit may be used in conjunction with DevB:0x3C[SBRST] to revert back to AGP 2.0 signaling. To do this, software should (1) set DevB:0x3C[SBRST] in order to reset the AGP card, (2) set 8XDIS to cause A_MB8XDET# to float high, and (3) clear DevB:0x3C[SBRST].

1TYPEDET: AGP voltage type detection. Read only. This bit reflects the state of the A_TYPEDET# pin. 0=The AGP master supports 1.5 volt signaling. 1=The AGP master requires 3.3 volt signaling and is therefore not compatible with the IC. If this bit is detected high by BIOS, an error should be signaled.

0DBIEN: dynamic bus inversion enable. Read-write. 1= A_DBI[H, L] enabled to dynamically invert the state of the A_AD signals when the IC is driving these. This only applies to AGP 3.0 transfers in the downstream direction (fast writes and read responses to AGP master requests). For PCI transfers in the downstream direction, A_DBI[H, L] are held inactive and no inversion takes place. 0=When the IC drives the A_AD lines, A_DBI[H, L] are driven low. Note: this bit is only valid when 8x transfer rates are enabled; if (1) DevA:0xA4[AGP3MD]=0 or (2) DevA:0xA4[AGP3MD]=1 and DevA:0xA8[DRATE] is not 010b, then this field is ignored and the DBI is not enabled.

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Contents Cover Device FeaturesOverview AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents System block diagram Configuration space Ball designations Rev 3.03 July 12List of Tables IO signal types Tunnel Link Signals AGP Signals ACALD, S and ACALD, S#. Compensation pins forSERR# and PERR# signals are not supported on the AGP bridge Test and Miscellaneous Signals Power and GroundPower Plane Sequencing Clocking Reset And InitializationFunctional Operation Overview Clock GatingAGP Tunnel LinksLink PHY Tags, UnitIDs, And OrderingVarious Behaviors Translation from AGP requests to link requestsAGP transaction Link transaction AGP Compensation And Calibration CyclesRegister Naming and Description Conventions Configuration SpaceRegisters Register Overview AGP Device AGP BridgeConfiguration spaces Memory mapped address spacesRegister attributes AGP Device Revision and Class Code Register DevA0x08 AGP Device Status And Command Register DevA0x04RESET# REVISION. Read onlyAGP Device Subsystem ID and Subsystem Vendor ID Register Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Capabilities PointerDefault 0000 0000h Attribute See below 24888 Rev 3.03 July 12AGP Miscellaneous Control Register DevA0x40 Nctl Pctl Updated by the hardware approximately every 8 microseconds1514 1Fh, then 1Fh is applied 11bBit Gart support. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Host translation#. This bit fixed lowRates AGP Command RegisterDefault 0000 0000h Attribute Read-write Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardAGP Control Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Aperture Size RegisterGartlo Gart base address register low Link Command RegisterGarthi Gart base address register high Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 0 Register DevA0xCC Link Frequency Capability 1 Register DevA0xD0Link Enumeration Scratchpad Register DevA0xD4 Default See below Attribute See below Behavior 3021 Reserved 2016Bctl Clock Control Register ActlSum exceeds 1Fh, then 1Fh is applied 11b Must be high. See .3.1 for detailsAGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x24. Default 0000 FFF0h Attribute Read-write Default 0000 00FFh Attribute See belowDevB0x3C Electrical Data Absolute Ratings Absolute maximum ratingsOperating ranges Operating RangesDC Characteristics Current and power consumptionDC characteristics for signals on the VDD33 power plane Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 Symbol Parameter Description Min Max Units AC data for common clock operation of AGP signalsAC Characteristics AC data for clocksAC data for clock-forwarded operation of AGP signals AGPBall Designations Top side viewSignal BGA positions Signal name BallPower and ground BGA positions Signal Ball NamePackage Specification Package mechanical drawingTest modes High Impedance ModeNand Tree Mode TestNand tree 2 output signal is STRAPL4 Appendix Revision History Revision

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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