AMD 8151 specifications Registers Register Overview, Configuration Space, AGP Device AGP Bridge

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

The first calibration cycle occurs approximately 4 milliseconds after the deassertion of RESET# (whether AGP 2.0 or 3.0 signaling is enabled).

5Registers

5.1Register Overview

The IC includes several sets of registers accessed through a variety of address spaces. IO address space refers to register addresses that are accessed through x86 IO instructions such as IN and OUT. PCI configuration space is typically accessed by the host through IO cycles to CF8h and CFCh. There is also memory space and indexed address space in the IC.

5.1.1Configuration Space

The address space for the IC configuration registers is broken up into busses, devices, functions, and, offsets, as defined by the link specification. It is accessed by HyperTransport™ technology-defined type 0 configuration cycles. The device number is mapped into bits[15:11] of the configuration address. The function number is mapped into bits[10:8] of the configuration address. The offset is mapped to bits[7:2] of the configuration address.

The following diagram shows the devices in configuration space as viewed by software.

Primary bus

 

 

 

 

 

 

 

AGP Device

AGP Bridge

 

 

DevA:0xXX

DevB:0xXX

 

 

Device header

Bridge header

 

 

First device

Second device

 

 

Function 0

Function 0

 

AGP Slot

 

 

 

 

Secondary bus

Figure 2: Configuration space.

Device A, above, is programmed to be the link base UnitID and device B is the link base UnitID plus 1.

5.1.2Register Naming and Description Conventions

Configuration register locations are referenced with mnemonics that take the form of Dev[AB]:[7:0]x[FF:0], where the first set of brackets contain the device number, the second set of brackets contain the function num- ber, and the last set of brackets contain the offset.

Other register locations (e.g. memory mapped registers) are referenced with an assigned mnemonic that speci- fies the address space and offset. These mnemonics start with two or three characters that identify the space followed by characters that identify the offset within the space.

Register fields within register locations are also identified with a name or bit group in brackets following the register location mnemonic.

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Contents Cover Device FeaturesOverview AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents System block diagram Configuration space Ball designations Rev 3.03 July 12List of Tables IO signal types Tunnel Link Signals AGP Signals ACALD, S and ACALD, S#. Compensation pins forSERR# and PERR# signals are not supported on the AGP bridge Power Plane Sequencing Test and Miscellaneous SignalsPower and Ground Clocking Reset And InitializationFunctional Operation Overview Clock GatingAGP Tunnel LinksLink PHY Tags, UnitIDs, And OrderingVarious Behaviors Translation from AGP requests to link requestsAGP transaction Link transaction AGP Compensation And Calibration CyclesRegister Naming and Description Conventions Configuration SpaceRegisters Register Overview AGP Device AGP BridgeRegister attributes Configuration spacesMemory mapped address spaces AGP Device Revision and Class Code Register DevA0x08 AGP Device Status And Command Register DevA0x04RESET# REVISION. Read onlyAGP Device Subsystem ID and Subsystem Vendor ID Register Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Capabilities PointerAGP Miscellaneous Control Register DevA0x40 Default 0000 0000h Attribute See below24888 Rev 3.03 July 12 Nctl Pctl Updated by the hardware approximately every 8 microseconds1514 1Fh, then 1Fh is applied 11bBit Gart support. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Host translation#. This bit fixed lowRates AGP Command RegisterDefault 0000 0000h Attribute Read-write Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardAGP Control Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Aperture Size RegisterGartlo Gart base address register low Link Command RegisterGarthi Gart base address register high Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Enumeration Scratchpad Register DevA0xD4 Link Frequency Capability 0 Register DevA0xCCLink Frequency Capability 1 Register DevA0xD0 Bctl Default See below Attribute See belowBehavior 3021 Reserved 2016 Clock Control Register ActlSum exceeds 1Fh, then 1Fh is applied 11b Must be high. See .3.1 for detailsAGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x3C DevB0x24. Default 0000 FFF0h Attribute Read-writeDefault 0000 00FFh Attribute See below Electrical Data Absolute Ratings Absolute maximum ratingsOperating ranges Operating RangesDC Characteristics Current and power consumptionDC characteristics for signals on the VDD33 power plane Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 Symbol Parameter Description Min Max Units AC data for common clock operation of AGP signalsAC Characteristics AC data for clocksAC data for clock-forwarded operation of AGP signals AGPBall Designations Top side viewSignal BGA positions Signal name BallPower and ground BGA positions Signal Ball NamePackage Specification Package mechanical drawingTest modes High Impedance ModeNand Tree Mode TestNand tree 2 output signal is STRAPL4 Appendix Revision History Revision

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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