AMD 8151 specifications Ball Designations, Top side view

Page 39

24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

7Ball Designations

 

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

 

A

 

 

LTACAD

LTACAD

LTACAD

LTACAD

LTACLK0

LTACLK0

LTACAD

LTACAD

LTACAD

LTACAD

LRACTL

LRACTL

LRACAD

LRACAD

LRACAD

LRACAD

LRACAD

LRACAD

LRACAD

LRACAD

 

 

A

 

 

 

_P0

_N0

_P2

_N2

_P

_N

_P5

_N5

_P7

_N7

_N

_P

_N6

_P6

_N4

_P4

_N3

_P3

_N1

_P1

 

 

 

B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

 

VDD12A

VSS

LTACAD

VDD18

LTACAD

VSS

LTACAD

VDD18

LTACAD

VSS

LTACTL_

VDD18

LRACAD

VSS

LRACAD

VDD18

LRACLK

VSS

LRACAD

VDD18

LRACAD

VDD12A

 

 

 

 

 

_P1

 

_P3

 

_P4

 

_P6

 

P

 

_N7

 

_N5

 

0_N

 

_N2

 

_N0

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

VDD12A

VSS

LTACAD

LTACAD

LTACAD

LTACAD

LTACLK1

LTACAD

LTACAD

LTACAD

LTACAD

LTACTL_

FREE4

LRACAD

LRACAD

LRACAD

LRACAD

LRACLK

LRACAD

LRACAD

LRACAD

LRACAD

VSS

VDD12A

 

 

 

_N8

_N1

_N10

_N3

_N

_N4

_N13

_N6

_N15

N

 

_P7

_P14

_P5

_P12

0_P

_P11

_P2

_P9

_P0

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

VSS

VDD12A

LTACAD

VDD18

LTACAD

VSS

LTACLK1

VDD18

LTACAD

VSS

LTACAD

VDD18

FREE5

VSS

LRACAD

VDD18

LRACAD

VSS

LRACAD

VDD18

LRACAD

VSS

VSS

VDD12A

 

 

 

_P8

 

_P10

 

_P

 

_P13

 

_P15

 

 

 

_N14

 

_N12

 

_N11

 

_N9

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

VDD12A

VSS

LTACAD

LTACAD

LTACAD

LTACAD

LTACAD

LTACAD

LTACAD

LTACAD

FREE7

FREE6

LRACAD

LRACAD

LRACAD

LRACAD

LRACLK

LRACLK

LRACAD

LRACAD

LRACAD

LRACAD

VDD12A

VSS

 

 

 

_P9

_N9

_P11

_N11

_P12

_N12

_P14

_N14

 

 

_N15

_P15

_N13

_P13

1_N

1_P

_N10

_P10

_N8

_P8

 

 

 

F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F

A_DBIH

VDD12A

VSS

VDD12A

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD12A

VSS

VDD12B

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

A_SBA0

A_DBIL

VDD12A

VDD12A

VDD12A

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD12A

VSS

VDD12B

VDD12B

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

A_SBA2

A_SBA1

STRAPL

VDD15

VSS

VDD12A

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD12A

VDD12A

VDD12A

VSS

VDD12B

VSS

VSS

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J

A_SBA3

VSS

STRAPL

STRAPL

STRAPL

VSS

VDD12A

VDD12A

VDD12A

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD12A

VSS

VDD12B

VDD12B

VDD12B

VSS

VDD18

LTBCAD

 

 

 

10

1

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P0

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

A_SB

A_SB

FREE1

A_GC8X

VSS

VDD15

VSS

VDD15

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD12B

VSS

VSS

VDD18

LTBCAD

LTBCAD

LTBCAD

 

STB_P

STB_N

 

DET#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_N1

_P1

_N0

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

A_SBA5

A_SBA4

VSS

A_GNT#

STRAPL

VSS

VDD15

VSS

VDD15

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

LTBCAD

LTBCAD

LTBCAD

VSS

LTBCAD

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P5

_P4

_N4

 

_P2

 

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

A_SBA6

VSS

STRAPL

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

LTBCAD

VSS

LTBCAD

LTBCAD

LTBCAD

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_N5

 

_N3

_P3

_N2

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

A_AD31

A_SBA7

NC1

A_REQ#

VSS

VSS

VDD15

VSS

VDD15

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

LTBCAD

LTBCAD

LTBCAD

VDD18

LTBCLK0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P7

_P6

_N6

 

_P

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

A_AD29

A_AD30

VSS

STRAPL

STRAPL

VDD15

VSS

VDD15

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

LTBCAD

VDD18

LTBCTL_

LTBCTL_

LTBCLK0

 

 

 

 

13

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_N7

 

N

P

_N

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

A_AD28

VSS

FREE2

VDD15

VSS

VSS

VDD15

VSS

VDD15

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

VSS

VDD18

LRBCAD

LRBCAD

LRBCAD

VSS

LRBCTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_N6

_N7

_P7

 

_N

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

A_AD26

A_AD27

FREE3

A_ST0

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD12B

VSS

VDD18

VSS

LRBCAD

VSS

LRBCLK

LRBCLK

LRBCTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P6

 

0_P

0_N

_P

 

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U

A_AD25

A_AD24

VSS

A_ST1

VSS

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VSS

VDD12B

VDD18

VSS

VDD18

LRBCAD

LRBCAD

LRBCAD

VDD18

LRBCAD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_N4

_N5

_P5

 

_N3

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

A_AD

VSS

A_ST2

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD12B

VSS

VDD18

VSS

LRBCAD

VDD18

LRBCAD

LRBCAD

LRBCAD

 

STB1_P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_P4

 

_P2

_N2

_P3

 

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

A_AD23

A_AD

A_CBE_

A_MB8X

VSS

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD15

VSS

VDD12B

VSS

VDD18

LDTCOM

LDTCOM

LDTCOM

VSS

LRBCAD

 

 

STB1_N

L3

DET#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P0

P1

P2

 

_N1

 

Y

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y

A_AD21

A_AD22

VSS

NC0

A_RBF#

VSS

A_CALS

STRAPL

STRAPL

VSS

STRAPL

STRAPL

STRAPL

VDD15

STRAPL

STRAPL

VSS

VDD12B

VSS

LDTCOM

VSS

LRBCAD

LRBCAD

LRBCAD

 

 

 

 

 

 

 

 

5

6

 

4

18

19

 

20

21

 

 

 

P3

 

_P0

_N0

_P1

 

AA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AA

A_AD20

VSS

STRAPL

VDD15

A_WBF#

A_CALD

VDD15

A_CALS

A_

VDD15

A_STOP

A_PAR

VDD15

STRAPL

A_PLL

STRAPL

TEST

VSS

VDD12B

VSS

VDD12B

VSS

VDD12B

VSS

 

 

 

14

 

 

 

 

#

FRAME#

 

#

 

 

3

CLKO

22

 

 

 

 

 

 

 

 

 

AB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AB

A_AD19

A_AD17

A_AD18

STRAPL

VSS

A_CALD

STRAPL

A_IRDY#

A_DEVS

A_TRDY

VSS

A_AD5

STRAPL

VSS

A_PLL

REFCLK

VSS

RESET#

VSS

VDD12B

VDD12B

VDD12B

VSS

VDD12B

 

 

 

 

15

 

#

16

 

EL#

#

 

 

2

 

CLKI

 

 

 

 

 

 

 

 

 

 

AC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AC

 

VSS

A_AD16

VSS

A_CBE_

A_AD14

VSS

A_AD12

A_AD9

VSS

A_AD

A_AD6

VSS

A_AD2

A_AD1

VSS

CMP

LDT-

A_PCLK

VSS

VDD33

VSS

VDD12B

 

 

 

 

 

 

L1

 

 

 

 

 

STB0_P

 

 

 

 

 

OVR

STOP#

 

 

 

 

 

 

 

AD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD

 

 

A_CBE_

STRAPL

A_AD15

A_AD13

A_AD11

A_AD10

A_AD8

A_CBE_

A_AD

A_AD7

A_AD4

A_AD3

A_AD0

A_REF

A_REF

PWROK

A_

A_TYPE

VDD33

VDDA18

 

 

 

 

 

L2

17

 

 

 

 

 

L0

STB0_N

 

 

 

 

GC

CG

 

RESET#

DET#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

 

Top side view.

Figure 3: Ball designations.

39

Image 39
Contents AMD-8151TMDevice Device FeaturesOverview CoverAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Test and Miscellaneous Signals Power and GroundPower Plane Sequencing Clock Gating Reset And InitializationFunctional Operation Overview ClockingTags, UnitIDs, And Ordering Tunnel LinksLink PHY AGPAGP Compensation And Calibration Cycles Translation from AGP requests to link requestsAGP transaction Link transaction Various BehaviorsAGP Device AGP Bridge Configuration SpaceRegisters Register Overview Register Naming and Description ConventionsConfiguration spaces Memory mapped address spacesRegister attributes REVISION. Read only AGP Device Status And Command Register DevA0x04RESET# AGP Device Revision and Class Code Register DevA0x08AGP Capabilities Pointer Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Device Subsystem ID and Subsystem Vendor ID RegisterDefault 0000 0000h Attribute See below 24888 Rev 3.03 July 12AGP Miscellaneous Control Register DevA0x40 Nctl 1Fh, then 1Fh is applied 11b Updated by the hardware approximately every 8 microseconds1514 PctlHost translation#. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Bit Gart support. This bit fixed lowPcalcyc and then DevA0xB0CALDIS should be cleared afterward AGP Command RegisterDefault 0000 0000h Attribute Read-write RatesAGP Aperture Size Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Control RegisterSlave/primary interface type. Read only Link Command RegisterGarthi Gart base address register high Gartlo Gart base address register lowLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 0 Register DevA0xCC Link Frequency Capability 1 Register DevA0xD0Link Enumeration Scratchpad Register DevA0xD4 Default See below Attribute See below Behavior 3021 Reserved 2016Bctl Must be high. See .3.1 for details ActlSum exceeds 1Fh, then 1Fh is applied 11b Clock Control RegisterAGP Bridge Revision and Class Code Register DevB0x08 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Vendor And Device ID Register DevB0x00AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x24. Default 0000 FFF0h Attribute Read-write Default 0000 00FFh Attribute See belowDevB0x3C Operating Ranges Absolute maximum ratingsOperating ranges Electrical Data Absolute RatingsSymbol Parameter Description Min Max Units Comments Current and power consumptionDC characteristics for signals on the VDD33 power plane DC CharacteristicsInput high voltage VDD15 + VDD15 AC data for clocks AC data for common clock operation of AGP signalsAC Characteristics Symbol Parameter Description Min Max UnitsAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationTest High Impedance ModeNand Tree Mode Test modesNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.