AMD 8151 specifications DevB0x24. Default 0000 FFF0h Attribute Read-write, DevB0x3C

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

DevB:0x24. Default: 0000 FFF0h

Attribute: Read-write.

Bits

Description

 

 

 

31:20

PMEMLIM. Prefetchable memory limit address bits[31:20]. See DevB:0x[30:1C] above.

 

 

 

19:16

Reserved.

 

 

 

15:4

PMEMBASE. Prefetchable memory base address bits[31:20]. See DevB:0x[30:1C] above.

 

 

 

3:0

Reserved.

 

 

 

 

DevB:0x30. Default: 0000 FFFFh

Attribute: Read-write.

Bits

Description

 

 

 

31:16

IOLIM. IO limit address bits[31:16]. See DevB:0x[30:1C] above.

 

 

15:0

IOBASE. IO base address bits[31:16]. See DevB:0x[30:1C] above.

 

 

 

AGP Bridge Interrupt and Bridge Control Register

DevB:0x3C

 

 

 

Default: 0000 00FFh

Attribute: See below.

Bits

Description

 

 

 

 

31:23

Reserved.

 

22SBRST: AGP bus reset. Read-write. 1=A_RESET# asserted; AGP bus placed into reset state. 0=A_RESET# not asserted.

21:20 Reserved.

19VGAEN: VGA decoding enable. Read-write. 1=Host-initiated commands targeting VGA- compatible address ranges are routed to the AGP bus. These include memory accesses from A0000h to BFFFFh (within the bottom megabyte of memory space only), IO accesses in which address bits[9:0] range from 3B0h to 3BBh or 3C0h to 3DFh (address bits[15:10] are not decoded, regardless of DevB:0x3C[ISAEN]; also this only applies to the first 64K of IO space; i.e., address bits[31:16] must be low). 0=The IC does not decode VGA-compatible address ranges.

18ISAEN: ISA decoding enable. Read-write. 1=The IO address window specified by DevB:0x1C[15:0] and DevB:0x30 is limited to the first 256 bytes of each 1K byte block specified; this only applies to the first 64K bytes of IO space. 0=The PCI IO window is the whole range specified by DevB:0x1C[15:0] and DevB:0x30.

17:16

Reserved.

15:8

INTERRUPT_PIN. Read; write once. These bits control no internal logic.

 

 

7:0

INTERRUPT_LINE. Read-write. These bits control no internal logic.

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Contents Overview Device FeaturesCover AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Test and Miscellaneous Signals Power and GroundPower Plane Sequencing Functional Operation Overview Reset And InitializationClocking Clock GatingLink PHY Tunnel LinksAGP Tags, UnitIDs, And OrderingAGP transaction Link transaction Translation from AGP requests to link requestsVarious Behaviors AGP Compensation And Calibration CyclesRegisters Register Overview Configuration SpaceRegister Naming and Description Conventions AGP Device AGP BridgeConfiguration spaces Memory mapped address spacesRegister attributes RESET# AGP Device Status And Command Register DevA0x04AGP Device Revision and Class Code Register DevA0x08 REVISION. Read onlyDefault 0000 00A0h Attribute Read only Default 0000 0000h Attribute Read write onceAGP Device Subsystem ID and Subsystem Vendor ID Register AGP Capabilities PointerDefault 0000 0000h Attribute See below 24888 Rev 3.03 July 12AGP Miscellaneous Control Register DevA0x40 Nctl 1514 Updated by the hardware approximately every 8 microsecondsPctl 1Fh, then 1Fh is applied 11bAGP Status Register AGP Revision and Capability RegisterBit Gart support. This bit fixed low Host translation#. This bit fixed lowDefault 0000 0000h Attribute Read-write AGP Command RegisterRates Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardAGP3MD Drate Default 0001 0F00h Attribute See belowAGP Control Register AGP Aperture Size RegisterGarthi Gart base address register high Link Command RegisterGartlo Gart base address register low Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 0 Register DevA0xCC Link Frequency Capability 1 Register DevA0xD0Link Enumeration Scratchpad Register DevA0xD4 Default See below Attribute See below Behavior 3021 Reserved 2016Bctl Sum exceeds 1Fh, then 1Fh is applied 11b ActlClock Control Register Must be high. See .3.1 for detailsAGP Bridge Status And Command Register DevB0x04 AGP Bridge Configuration RegistersAGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x24. Default 0000 FFF0h Attribute Read-write Default 0000 00FFh Attribute See belowDevB0x3C Operating ranges Absolute maximum ratingsElectrical Data Absolute Ratings Operating RangesDC characteristics for signals on the VDD33 power plane Current and power consumptionDC Characteristics Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 AC Characteristics AC data for common clock operation of AGP signalsSymbol Parameter Description Min Max Units AC data for clocksAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationNand Tree Mode High Impedance ModeTest modes TestNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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