AMD 8151 specifications Link Configuration And Control Register

Page 25

24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

26MASHST: master host. Read; set and cleared by hardware. This bit indicates which link is the path to the master (or only) host bridge on the HyperTransport™ technology chain. 1=The hardware set this bit as a result of a write command from the B side of the tunnel to any of the bytes of DevA:0xC0[31:16]. 0=The hardware cleared this bit as a result of a write command from the A side of the tunnel to any of the bytes of DevA:0xC0[31:16]. This bit, along with DEFDIR, is used to determine the side of the tunnel to which AGP master requests are sent.

25:21

UnitID count. Read only. Specifies the number of UnitIDs used by the IC (three).

20:16

BUID: base UnitID. Read-write. This specifies the link-protocol base UnitID. The IC's logic uses

 

this value to determine the UnitIDs for link request and response packets. When a new value is

 

written to this field, the response includes a UnitID that is based on the new value in this register.

 

Note: some legacy operating systems may require that this value be set to zero for normal operation

 

so that the AGP capability block is part of device 0. Since the IC does not use the base unit ID in any

 

link transactions, there is no conflict with the host unit ID. However, at boot, BIOS is required to

 

temporarily change the BUID value of the IC so that the BUID values in downstream devices may be

 

initialized. After downstream BUID values are initialized, this field may be set to zero to be

 

compatible with legacy operating systems.

 

 

 

 

15:8

Reserved.

 

 

 

7:0

Capabilities ID. Read only. Specifies the capabilities ID for link configuration space.

 

 

Link Configuration And Control Register

DevA:0xC4 and DevA:0xC8

 

 

 

DevA:0xC4 applies side A of the tunnel and DevA:0xC8 applies to side B of the tunnel. The default value for bit[5] may vary (see the definition).

Default: ??11 0020h for DevA:0xC4 and ??00 0020h for DevA:0xC8.Attribute: See below.

Bits

Description

 

 

31

Reserved.

 

 

30:28

LWO: link width out. Read-write. Specifies the operating width of the outgoing link. Legal values

 

are 001b (16 bits; DevA:0xC4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not

 

connected). Note: this field is cleared by PWROK reset but not by RESET#; the default value of this

 

field depends on the widths of the links of the connecting device, per the link specification. Note:

 

after this field is updated, the link width does not change until either RESET# is asserted or a link

 

disconnect sequence occurs through or LDTSTOP#.

 

 

27

Reserved.

 

 

26:24

LWI: link width in. Read-write. Specifies the operating width of the incoming link. Legal values are

 

001b (16 bits; DevA:0xC4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not connected).

 

Note: this field is cleared by PWROK reset but not by RESET#; the default value of this field depends

 

on the widths of the links of the connecting device, per the link specification. Note: after this field is

 

updated, the link width does not change until either RESET# is asserted or a link disconnect sequence

 

occurs through an LDTSTOP# assertion.

 

 

23

Reserved.

 

 

22:20

Max link width out. Read only. This specifies the width of the outgoing link to be 16 bits wide for

 

side A and 8 bits wide for side B.

 

 

19

Reserved.

 

 

25

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Contents Overview Device FeaturesCover AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Power and Ground Test and Miscellaneous SignalsPower Plane Sequencing Functional Operation Overview Reset And InitializationClocking Clock GatingLink PHY Tunnel LinksAGP Tags, UnitIDs, And OrderingAGP transaction Link transaction Translation from AGP requests to link requestsVarious Behaviors AGP Compensation And Calibration CyclesRegisters Register Overview Configuration SpaceRegister Naming and Description Conventions AGP Device AGP BridgeMemory mapped address spaces Configuration spacesRegister attributes RESET# AGP Device Status And Command Register DevA0x04AGP Device Revision and Class Code Register DevA0x08 REVISION. Read onlyDefault 0000 00A0h Attribute Read only Default 0000 0000h Attribute Read write onceAGP Device Subsystem ID and Subsystem Vendor ID Register AGP Capabilities Pointer24888 Rev 3.03 July 12 Default 0000 0000h Attribute See belowAGP Miscellaneous Control Register DevA0x40 Nctl 1514 Updated by the hardware approximately every 8 microsecondsPctl 1Fh, then 1Fh is applied 11bAGP Status Register AGP Revision and Capability RegisterBit Gart support. This bit fixed low Host translation#. This bit fixed lowDefault 0000 0000h Attribute Read-write AGP Command RegisterRates Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardAGP3MD Drate Default 0001 0F00h Attribute See belowAGP Control Register AGP Aperture Size RegisterGarthi Gart base address register high Link Command RegisterGartlo Gart base address register low Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 1 Register DevA0xD0 Link Frequency Capability 0 Register DevA0xCCLink Enumeration Scratchpad Register DevA0xD4 Behavior 3021 Reserved 2016 Default See below Attribute See belowBctl Sum exceeds 1Fh, then 1Fh is applied 11b ActlClock Control Register Must be high. See .3.1 for detailsAGP Bridge Status And Command Register DevB0x04 AGP Bridge Configuration RegistersAGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved Default 0000 00FFh Attribute See below DevB0x24. Default 0000 FFF0h Attribute Read-writeDevB0x3C Operating ranges Absolute maximum ratingsElectrical Data Absolute Ratings Operating RangesDC characteristics for signals on the VDD33 power plane Current and power consumptionDC Characteristics Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 AC Characteristics AC data for common clock operation of AGP signalsSymbol Parameter Description Min Max Units AC data for clocksAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationNand Tree Mode High Impedance ModeTest modes TestNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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