AMD 8151 specifications Link Frequency Capability 0 Register DevA0xCC

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

Link Frequency Capability 0 Register

DevA:0xCC

Default: 0035 0022h.

Attribute: See below.

Bits

Description

 

 

 

31:16

FREQCAPA: link A frequency capability. Read only. These bits indicate that A side of the tunnel

 

supports 200, 400, 600, and 800 MHz link frequencies.

 

 

 

15:12

Reserved.

 

 

 

11:8

FREQA: link A frequency. Read-write. Specifies the link side A frequency. Legal values are 0h (200

 

MHz), 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: this bit is cleared by PWROK reset,

 

not by RESET#. Note: after this field is updated, the link frequency does not change until either

 

RESET# is asserted or a link disconnect sequence occurs through LDTSTOP#.

 

 

7:0

REVISION. Read only. Revision A of the IC is designed to version 1.02 of the link specification.

 

 

 

Link Frequency Capability 1 Register

DevA:0xD0

 

 

 

Default: 0035 0002h.

Attribute: See below.

Bits

Description

 

 

 

31:16

FREQCAPB: link B frequency capability. Read only. These bits indicate that that B side of the

 

tunnel supports 200, 400, 600, and 800 MHz link frequencies.

 

 

 

15:12

Reserved.

 

 

 

11:8

FREQB: link B frequency. Read-write. Specifies the link side B frequency. Legal values are 0h (200

 

MHz), and 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: although it is possible to program

 

this field for higher frequencies, the B link of the IC is only designed to support 200 and 400 MHz

 

operation. Note: this bit is cleared by PWROK reset, not by RESET#. Note: after this field is updated,

 

the link frequency does not change until either RESET# is asserted or a link disconnect sequence

 

occurs through LDTSTOP#.

 

 

 

7:0

Link device feature capability indicator. Read only. These bits are set to indicate that the IC

 

supports LDTSTOP#.

 

 

 

 

Link Enumeration Scratchpad Register

DevA:0xD4

 

 

 

Default: 0000 0000h.

Attribute: See below.

Bits

Description

 

 

 

 

31:16

Reserved.

 

 

 

15:0

ESP: enumeration scratchpad. Read-write. This field controls no hardware within the IC. Note: this

 

bit is cleared by PWROK reset, not by RESET#.

 

 

 

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Contents AMD-8151TMDevice Device FeaturesOverview CoverAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Test and Miscellaneous Signals Power and GroundPower Plane Sequencing Clock Gating Reset And InitializationFunctional Operation Overview ClockingTags, UnitIDs, And Ordering Tunnel LinksLink PHY AGPAGP Compensation And Calibration Cycles Translation from AGP requests to link requestsAGP transaction Link transaction Various BehaviorsAGP Device AGP Bridge Configuration SpaceRegisters Register Overview Register Naming and Description ConventionsConfiguration spaces Memory mapped address spacesRegister attributes REVISION. Read only AGP Device Status And Command Register DevA0x04RESET# AGP Device Revision and Class Code Register DevA0x08AGP Capabilities Pointer Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Device Subsystem ID and Subsystem Vendor ID RegisterDefault 0000 0000h Attribute See below 24888 Rev 3.03 July 12AGP Miscellaneous Control Register DevA0x40 Nctl 1Fh, then 1Fh is applied 11b Updated by the hardware approximately every 8 microseconds1514 PctlHost translation#. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Bit Gart support. This bit fixed lowPcalcyc and then DevA0xB0CALDIS should be cleared afterward AGP Command RegisterDefault 0000 0000h Attribute Read-write RatesAGP Aperture Size Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Control RegisterSlave/primary interface type. Read only Link Command RegisterGarthi Gart base address register high Gartlo Gart base address register lowLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 0 Register DevA0xCC Link Frequency Capability 1 Register DevA0xD0Link Enumeration Scratchpad Register DevA0xD4 Default See below Attribute See below Behavior 3021 Reserved 2016Bctl Must be high. See .3.1 for details ActlSum exceeds 1Fh, then 1Fh is applied 11b Clock Control RegisterAGP Bridge Revision and Class Code Register DevB0x08 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Vendor And Device ID Register DevB0x00AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x24. Default 0000 FFF0h Attribute Read-write Default 0000 00FFh Attribute See belowDevB0x3C Operating Ranges Absolute maximum ratingsOperating ranges Electrical Data Absolute RatingsSymbol Parameter Description Min Max Units Comments Current and power consumptionDC characteristics for signals on the VDD33 power plane DC CharacteristicsInput high voltage VDD15 + VDD15 AC data for clocks AC data for common clock operation of AGP signalsAC Characteristics Symbol Parameter Description Min Max UnitsAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationTest High Impedance ModeNand Tree Mode Test modesNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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