AMD 8151 AGP Bridge Configuration Registers, AGP Bridge Vendor And Device ID Register DevB0x00

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

5.3AGP Bridge Configuration Registers

These registers are located in PCI configuration space, in the second device (device B), function 0. See section 5.1.2 for a description of the register naming convention.

AGP Bridge Vendor And Device ID Register

DevB:0x00

Default: 7455 1022h

Attribute: See below.

Bits

Description

 

 

 

31:16

AGP bridge device ID. Bits[31:20] are read only; bits[19:16] are write-once. When the LSBs are left

 

at the default value, some operating systems may load a generic graphics driver. System BIOS should

 

program the LSBs to 6h in order to circumvent the loading of such a driver.

 

 

 

15:0

Vendor ID. Read only.

 

 

 

 

AGP Bridge Status And Command Register

DevB:0x04

 

 

 

Default: 0220 0000h

Attribute: See below.

Bits

Description

 

 

 

31:9

Read only. These bits are fixed in their default state.

 

 

8

SERREN: SERR# enable. Read-write. This bit controls no hardware.

 

 

7:3

Special cycle enable. Read only. This bit is hardwired low.

 

 

2

MASEN: PCI master enable. Read-write. 1=Enables the AGP bus master to initiate PCI cycles to

 

the host.

 

 

 

1

MEMEN: memory enable. Read-write. 1=Enables access to the AGP bus memory space.

 

 

0

IOEN: IO enable. Read-write. 1=Enables access to the AGP bus IO space.

 

 

 

AGP Bridge Revision and Class Code Register

DevB:0x08

 

 

 

Default: 0604 00??h

Attribute: Read only.

Bits

Description

 

 

 

 

31:8

CLASSCODE.

 

 

 

 

7:0

REVISION.

 

 

 

 

AGP Bridge BIST-Header-Latency-Cache Register

DevB:0x0C

 

 

 

Default: 0001 0000h

Attribute: See below.

Bits

Description

 

 

 

31:24

BIST. Read only. These bits fixed at their default values.

 

 

23:16

HEADER. Read only. These bits fixed at their default values.

 

 

 

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Contents Cover Device FeaturesOverview AMD-8151TMDeviceAMD-8151 TM AGP Tunnel Data Sheet Table of Contents System block diagram Configuration space Ball designations Rev 3.03 July 12List of Tables IO signal types Tunnel Link Signals AGP Signals ACALD, S and ACALD, S#. Compensation pins forSERR# and PERR# signals are not supported on the AGP bridge Test and Miscellaneous Signals Power and GroundPower Plane Sequencing Clocking Reset And InitializationFunctional Operation Overview Clock GatingAGP Tunnel LinksLink PHY Tags, UnitIDs, And OrderingVarious Behaviors Translation from AGP requests to link requestsAGP transaction Link transaction AGP Compensation And Calibration CyclesRegister Naming and Description Conventions Configuration SpaceRegisters Register Overview AGP Device AGP BridgeConfiguration spaces Memory mapped address spacesRegister attributes AGP Device Revision and Class Code Register DevA0x08 AGP Device Status And Command Register DevA0x04RESET# REVISION. Read onlyAGP Device Subsystem ID and Subsystem Vendor ID Register Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Capabilities PointerDefault 0000 0000h Attribute See below 24888 Rev 3.03 July 12AGP Miscellaneous Control Register DevA0x40 Nctl Pctl Updated by the hardware approximately every 8 microseconds1514 1Fh, then 1Fh is applied 11bBit Gart support. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Host translation#. This bit fixed lowRates AGP Command RegisterDefault 0000 0000h Attribute Read-write Pcalcyc and then DevA0xB0CALDIS should be cleared afterwardAGP Control Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Aperture Size RegisterGartlo Gart base address register low Link Command RegisterGarthi Gart base address register high Slave/primary interface type. Read onlyLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 0 Register DevA0xCC Link Frequency Capability 1 Register DevA0xD0Link Enumeration Scratchpad Register DevA0xD4 Default See below Attribute See below Behavior 3021 Reserved 2016Bctl Clock Control Register ActlSum exceeds 1Fh, then 1Fh is applied 11b Must be high. See .3.1 for detailsAGP Bridge Vendor And Device ID Register DevB0x00 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Revision and Class Code Register DevB0x08AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x24. Default 0000 FFF0h Attribute Read-write Default 0000 00FFh Attribute See belowDevB0x3C Electrical Data Absolute Ratings Absolute maximum ratingsOperating ranges Operating RangesDC Characteristics Current and power consumptionDC characteristics for signals on the VDD33 power plane Symbol Parameter Description Min Max Units CommentsInput high voltage VDD15 + VDD15 Symbol Parameter Description Min Max Units AC data for common clock operation of AGP signalsAC Characteristics AC data for clocksAC data for clock-forwarded operation of AGP signals AGPBall Designations Top side viewSignal BGA positions Signal name BallPower and ground BGA positions Signal Ball NamePackage Specification Package mechanical drawingTest modes High Impedance ModeNand Tree Mode TestNand tree 2 output signal is STRAPL4 Appendix Revision History Revision

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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