AMD 8151 specifications Rev 3.03 July 12, AGP Bridge Memory Base-Limit Registers DevB0x301C

Page 31

24888 Rev 3.03 - July 12, 2004

 

AMD-8151TMAGP Tunnel Data Sheet

 

 

 

15:8

LATENCY. Read-write. These bits control no hardware.

 

 

 

 

7:0

CACHE. Read only. These bits fixed at their default values.

 

 

 

 

AGP Bridge Bus Numbers And Secondary Latency Register

DevB:0x18

 

 

 

Default: 0000 0000h

Attribute: Read-write.

Bits

Description

 

 

 

 

31:24

SECLAT. Secondary latency timer. These bits control no hardware.

 

 

 

 

23:16

SUBBUS. Subordinate bus number.

 

 

 

 

 

 

15:8

SECBUS. Secondary bus number.

 

 

 

 

 

 

7:0

PRIBUS. Primary bus number.

 

 

 

 

 

 

AGP Bridge Memory Base-Limit Registers

 

DevB:0x[30:1C]

 

 

 

 

These registers specify the IO-space (DevB:0x1C and DevB:0x30), non-prefetchable memory-space (DevB:0x20), and prefetchable memory-space (DevB:0x24) address windows for transactions that are mapped from the 40-bit link address space to the AGP bus.

The links support 25 bits of IO space. AGP supports 32 bits of IO space. Host accesses to the link-defined IO region are mapped to the AGP IO window with the 7 MSB always zero. AGP IO accesses in which any of the

7 MSBs are other than zero are ignored. The AGP IO space window is defined as follow:

AGP IO window =

{7'h00, DevB:30[24:16], DevB:0x1C[15:12], 12'hFFF} >= address >= {7'h00, DevB:30[8:0], DevB:0x1C[7:4], 12'h000};

The links support 40 bits of memory space. AGP supports 32 bits of non-prefetchable memory space. The AGP non-prefetchable window is defined to be within the lowest 4 gigabytes of link address space. AGP accesses above 4 gigabytes cannot access non-prefetchable memory space. The AGP non-prefetchable memory space window is defined as follows:

AGP non-prefetchable memory window =

{32'h00, DevB:0x20[31:20], 20'hF_FFFF} >= address >= {32'h00, DevB:0x20[15:4], 20'h0_0000};

The links support 40 bits of memory space. AGP supports 32 bits of prefetchable memory space. The AGP prefetchable window is defined to be within the lowest 4 gigabytes of link address space. The AGP prefetch- able memory space window is defined as follows:

AGP prefetchable memory window =

{32'h00, DevB:0x24[31:20], 20'hF_FFFF} >= address >= {32'h00, DevB:0x24[15:4], 20'h0_0000};

These windows may also be altered by DevB:0x3C[VGAEN, ISAEN]. When the address (from either the host or from an AGP bus master) is inside one of the windows, then the transaction targets the AGP bus. Therefore, the following transactions are possible:

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Contents AMD-8151TMDevice Device FeaturesOverview CoverAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Power and Ground Test and Miscellaneous SignalsPower Plane Sequencing Clock Gating Reset And InitializationFunctional Operation Overview ClockingTags, UnitIDs, And Ordering Tunnel LinksLink PHY AGPAGP Compensation And Calibration Cycles Translation from AGP requests to link requestsAGP transaction Link transaction Various BehaviorsAGP Device AGP Bridge Configuration SpaceRegisters Register Overview Register Naming and Description ConventionsMemory mapped address spaces Configuration spacesRegister attributes REVISION. Read only AGP Device Status And Command Register DevA0x04RESET# AGP Device Revision and Class Code Register DevA0x08AGP Capabilities Pointer Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Device Subsystem ID and Subsystem Vendor ID Register24888 Rev 3.03 July 12 Default 0000 0000h Attribute See belowAGP Miscellaneous Control Register DevA0x40 Nctl 1Fh, then 1Fh is applied 11b Updated by the hardware approximately every 8 microseconds1514 PctlHost translation#. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Bit Gart support. This bit fixed lowPcalcyc and then DevA0xB0CALDIS should be cleared afterward AGP Command RegisterDefault 0000 0000h Attribute Read-write RatesAGP Aperture Size Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Control RegisterSlave/primary interface type. Read only Link Command RegisterGarthi Gart base address register high Gartlo Gart base address register lowLink Configuration And Control Register Rev 3.03 July 12 Link Frequency Capability 1 Register DevA0xD0 Link Frequency Capability 0 Register DevA0xCCLink Enumeration Scratchpad Register DevA0xD4 Behavior 3021 Reserved 2016 Default See below Attribute See belowBctl Must be high. See .3.1 for details ActlSum exceeds 1Fh, then 1Fh is applied 11b Clock Control RegisterAGP Bridge Revision and Class Code Register DevB0x08 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Vendor And Device ID Register DevB0x00AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved Default 0000 00FFh Attribute See below DevB0x24. Default 0000 FFF0h Attribute Read-writeDevB0x3C Operating Ranges Absolute maximum ratingsOperating ranges Electrical Data Absolute RatingsSymbol Parameter Description Min Max Units Comments Current and power consumptionDC characteristics for signals on the VDD33 power plane DC CharacteristicsInput high voltage VDD15 + VDD15 AC data for clocks AC data for common clock operation of AGP signalsAC Characteristics Symbol Parameter Description Min Max UnitsAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationTest High Impedance ModeNand Tree Mode Test modesNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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