AMD 8151 Functional Operation Overview, Reset And Initialization, Clocking, Clock Gating

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

4Functional Operation

4.1Overview

The IC connects to the host through either the side A or side B HyperTransportTM link interface. The other side of the tunnel may or may not be connected to another device. Host-initiated transactions that do not target the IC or the bridge flow through the tunnel to the downstream device. Transactions claimed by the device are passed to internal registers or to the AGP bridge.

See section 5.1 for details about the software view of the IC. See section 5.1.2 for a description of the register naming convention. See the AMD-8151TMHyperTransportTM AGP3.0 Graphics Tunnel Design Guide for addi- tional information.

4.2Reset And Initialization

RESET# and PWROK are both required to be low while the power planes to the IC are invalid and for at least 1 millisecond after the power planes are valid. Deassertion of PWROK is referred to as a cold reset. After PWROK is brought high, RESET# is required to stay low for at least 1 additional millisecond. After RESET# is brought high, the links go through the initialization sequence.

After a cold reset, the IC may be reset by asserting RESET# while PWROK remains high. This is referred to as a warm reset. RESET# must be asserted for no less than 1 millisecond during a warm reset.

4.3Clocking

It is required that REFCLK be valid in order for the IC to operate. Also, the LR[B, A]CLK inputs from the operation links must also be valid at the frequency defined DevA:0xCC[FREQA] and DevA:0xD0[FREQB]. The IC provides A_PCLK as the clock to the AGP device.

The systemboard is required to include a connection from A_PLLCLKO to A_PLLCLKI. The length of this connection is required to be approximately the same as length of the A_PCLK trace from the IC to the external AGP devices (including approximately 2.5 inches of etch on the AGP card). The IC uses this loopback to help match the external trace delay.

4.3.1Clock Gating

Internal clocks may be disabled during power-managed system states such as power-on suspend. It is required that all upstream requests initiated by the IC be suspended while in this state.

To enable clock gating, DevA:0xF0[ICGSMAF] is programmed to the values in which clock gating will be enabled. Stop Grant cycles and STPCLK deassertion link broadcasts interact to define the window in which the IC is enabled for clock gating during LDTSTOP# assertions. The system is placed into power managed states by steps that include a broadcast over the links of the Stop Grant cycle that includes the System Management Action Field (SMAF) followed by the assertion of LDTSTOP#. When the IC detects the Stop Grant broadcast which is enabled for clock gating, it enables clock gating for the next assertion of LDTSTOP#. While exiting the power-managed state, the system is required to broadcast a STPCLK deassertion message. The IC uses this message to disable clock gating during LDTSTOP# assertions. This is important because an LDTSTOP# asser- tion is not guaranteed to occur after the Stop Grant broadcast is received. The clock gating window must be closed to insure that clock gating does not occur during Stop Grant for LDTSTOP# assertions that are not asso- ciated with the power states specified by DevA:0xF0[ICGSMAF].

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Contents AMD-8151TMDevice Device FeaturesOverview CoverAMD-8151 TM AGP Tunnel Data Sheet Table of Contents Rev 3.03 July 12 System block diagram Configuration space Ball designationsList of Tables IO signal types Tunnel Link Signals ACALD, S and ACALD, S#. Compensation pins for AGP SignalsSERR# and PERR# signals are not supported on the AGP bridge Power Plane Sequencing Test and Miscellaneous SignalsPower and Ground Clock Gating Reset And InitializationFunctional Operation Overview ClockingTags, UnitIDs, And Ordering Tunnel LinksLink PHY AGPAGP Compensation And Calibration Cycles Translation from AGP requests to link requestsAGP transaction Link transaction Various BehaviorsAGP Device AGP Bridge Configuration SpaceRegisters Register Overview Register Naming and Description ConventionsRegister attributes Configuration spacesMemory mapped address spaces REVISION. Read only AGP Device Status And Command Register DevA0x04RESET# AGP Device Revision and Class Code Register DevA0x08AGP Capabilities Pointer Default 0000 0000h Attribute Read write onceDefault 0000 00A0h Attribute Read only AGP Device Subsystem ID and Subsystem Vendor ID RegisterAGP Miscellaneous Control Register DevA0x40 Default 0000 0000h Attribute See below24888 Rev 3.03 July 12 Nctl 1Fh, then 1Fh is applied 11b Updated by the hardware approximately every 8 microseconds1514 PctlHost translation#. This bit fixed low AGP Revision and Capability RegisterAGP Status Register Bit Gart support. This bit fixed lowPcalcyc and then DevA0xB0CALDIS should be cleared afterward AGP Command RegisterDefault 0000 0000h Attribute Read-write RatesAGP Aperture Size Register Default 0001 0F00h Attribute See belowAGP3MD Drate AGP Control RegisterSlave/primary interface type. Read only Link Command RegisterGarthi Gart base address register high Gartlo Gart base address register lowLink Configuration And Control Register Rev 3.03 July 12 Link Enumeration Scratchpad Register DevA0xD4 Link Frequency Capability 0 Register DevA0xCCLink Frequency Capability 1 Register DevA0xD0 Bctl Default See below Attribute See belowBehavior 3021 Reserved 2016 Must be high. See .3.1 for details ActlSum exceeds 1Fh, then 1Fh is applied 11b Clock Control RegisterAGP Bridge Revision and Class Code Register DevB0x08 AGP Bridge Configuration RegistersAGP Bridge Status And Command Register DevB0x04 AGP Bridge Vendor And Device ID Register DevB0x00AGP Bridge Memory Base-Limit Registers DevB0x301C 3130 Reserved DevB0x3C DevB0x24. Default 0000 FFF0h Attribute Read-writeDefault 0000 00FFh Attribute See below Operating Ranges Absolute maximum ratingsOperating ranges Electrical Data Absolute RatingsSymbol Parameter Description Min Max Units Comments Current and power consumptionDC characteristics for signals on the VDD33 power plane DC CharacteristicsInput high voltage VDD15 + VDD15 AC data for clocks AC data for common clock operation of AGP signalsAC Characteristics Symbol Parameter Description Min Max UnitsAGP AC data for clock-forwarded operation of AGP signalsTop side view Ball DesignationsSignal name Ball Signal BGA positionsSignal Ball Name Power and ground BGA positionsPackage mechanical drawing Package SpecificationTest High Impedance ModeNand Tree Mode Test modesNand tree 2 output signal is STRAPL4 Revision Appendix Revision History

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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