Maxim MAX12557 manual Pin Description, PIN Name Function, Same side of the PC board

MAX12557

Dual, 65Msps, 14-Bit, IF/Baseband ADC

			Pin Description
	PIN	NAME	FUNCTION
1, 4, 5, 9,		GND	Converter Ground. Connect all ground pins and the exposed paddle (EP) together.
13, 14, 17
2		INAP	Channel A Positive Analog Input
3		INAN	Channel A Negative Analog Input
6		COMA	Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.
			Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass
7		REFAP	REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
			and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
			same side of the PC board.
			Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass
8		REFAN	REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
			and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
			same side of the PC board.
			Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass
10		REFBN	REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
			and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
			same side of the PC board.
			Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass
11		REFBP	REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
			and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
			same side of the PC board.
12		COMB	Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.
15		INBN	Channel B Negative Analog Input
16		INBP	Channel B Positive Analog Input
			Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock
18		DIFFCLK/	input drives.
		SECLK	DIFFCLK/SECLK = GND: Selects single-ended clock input drive.
			DIFFCLK/SECLK = OVDD: Selects differential clock input drive.
19		CLKN	Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential
			clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
			the clock signal to CLKP and connect CLKN to GND.
20		CLKP	Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential
			clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
			the single-ended clock signal to CLKP and connect CLKN to GND.
21		DIV2	Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.
22		DIV4	Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.
	23–26, 61,	VDD	Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel
62, 63			capacitor combination of ≥10µF and 0.1µF. Connect all VDD pins to the same potential.
27, 43, 60		OVDD	Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
			parallel capacitor combination of ≥10µF and 0.1µF.

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