Maxim MAX12557 manual Functional Diagram

Page 15

Dual, 65Msps, 14-Bit, IF/Baseband ADC

			CLOCK
	INAP	14-BIT	DIGITAL	DATA	OUTPUT	D0A TO D13A
	T/H	PIPELINE	ERROR	DATA	OUTPUT
	T/H	PIPELINE	ERROR	FORMAT	DRIVERS
	INAN	ADC	CORRECTION	FORMAT	DRIVERS	DORA
	INAN	ADC	CORRECTION			DORA
	REFAP	CHANNEL A
	COMA	REFERENCE	MAX12557
	REFAN	SYSTEM
	REFAN
						G/T
	REFIN		INTERNAL
			INTERNAL
	REFOUT		REFERENCE			DAV
			GENERATOR
	SHREF
	REFBP	CHANNEL B				OVDD
	REFBP	CHANNEL B
	COMB	REFERENCE
	REFBN	SYSTEM
	REFBN
	INBP	14-BIT	DIGITAL	DATA	OUTPUT	D0B TO D13B
	T/H	PIPELINE	ERROR	DATA	OUTPUT
	T/H	PIPELINE	ERROR	FORMAT	DRIVERS
	INBN	ADC	CORRECTION	FORMAT	DRIVERS	DORB
	INBN	ADC	CORRECTION			DORB
			CLOCK
	DIFFCLK/SECLK					VDD
	DIFFCLK/SECLK
	CLKP		CLOCK		POWER
					POWER
		CLOCK	DUTY-CYCLE		CONTROL	PD
		CLOCK	DUTY-CYCLE		CONTROL
		DIVIDER	EQUALIZER		AND
	CLKN	DIVIDER	EQUALIZER		AND
	CLKN				BIAS CIRCUITS
					BIAS CIRCUITS
	DIV2					GND
	DIV2
	DIV4

MAX12557

Figure 2. Functional Diagram

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Image 15

Contents Ordering Information FeaturesGeneral Description ApplicationsConversion Rate Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Analog Input INAP, INAN, INBP, InbnParameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND DIFFCLK/ Seclk = OV DDDIFFCLK/SECLK = Ovdd Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = GNDTypical Operating Characteristics Timing Characteristics FigureFFT Plot 32,768-POINT Data Record TWO-TONE IMD Plot 16,384-POINT Data Record MAX12557FIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock SpeedSNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital Vs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHzGain Error vs. Temperature Pin Description PIN Name FunctionSame side of the PC board D3B D0BD1B D2BRefin Detailed DescriptionShref RefoutFunctional Diagram Reference Output Reference ConfigurationsReference Mode Analog Inputs and Input Track-and-Hold T/H AmplifierClock Input and Clock Control Lines Clock Duty-Cycle EqualizerSystem Timing Requirements Data-Valid OutputDIV4 DIV2 Function Output Codes vs. Input Voltage Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12557 Grounding, Bypassing, and Board LayoutParameter Definitions Total Harmonic Distortion THD Aperture DelayFull-Power Bandwidth Overdrive Recovery TimePin Configuration Gain MatchingOffset Matching 68L QFN THIN.EPS Package Information