Maxim MAX12557 manual FCLK = 65.00352MHz, fIN = 175MHz, PDISS, Iovdd Digital

Page 10

Dual, 65Msps, 14-Bit, IF/Baseband ADC

Typical Operating Characteristics (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 175MHz)

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 70MHz)

(fCLK = 65.00352MHz, fIN = 70MHz)

MAX12557

-THD, SFDR (dBc)

85

 

MAX12557 toc22

80

SFDR

 

 

 

75

 

 

-THD

70

65

60

3.0

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

 

80

 

 

 

 

 

 

toc23

 

95

 

 

 

 

 

 

 

 

 

 

 

76

 

 

SNR

 

 

 

MAX12557

 

90

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(dB)

 

 

 

 

 

 

 

 

(dBc)

85

72

 

 

 

 

 

 

 

80

SINAD

 

 

SINAD

 

 

 

 

SFDR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

75

SNR,

68

 

 

 

 

 

 

 

-THD,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

 

64

 

 

 

 

 

 

 

 

65

 

 

 

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

3.6

 

60

 

1.5

1.8

2.1

2.4

2.7

3.0

3.3

 

 

 

 

 

 

OVDD (V)

 

 

 

 

 

SFDR

toc24

MAX12557

 

-THD

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

 

 

 

OVDD (V)

 

 

 

SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE

-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE

PDISS, IVDD (ANALOG) vs. ANALOG SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 175MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

 

75

 

 

SNR

 

 

 

toc25

 

80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX12557

 

 

 

72

 

 

 

 

 

 

 

76

 

 

 

 

 

 

 

 

 

(dB)

69

 

 

 

 

 

 

 

(dBc)

72

SINAD

 

 

 

 

 

 

 

SFDR

 

 

 

SINAD

 

 

 

 

SNR,

66

 

 

 

 

 

 

 

-THD,

68

 

 

 

 

 

 

 

 

 

 

63

 

 

 

 

 

 

 

 

64

 

60

 

 

 

 

 

 

3.6

 

60

 

1.5

1.8

2.1

2.4

2.7

3.0

3.3

 

 

 

 

 

 

OVDD (V)

 

 

 

 

 

 

 

 

 

 

 

 

toc26

900

 

 

 

 

 

 

 

 

 

 

 

 

SFDR

 

 

MAX12557

800

 

 

 

 

 

 

 

 

 

 

 

 

 

 

700

 

 

 

 

 

 

 

mA)

 

 

 

 

 

 

 

600

 

 

 

 

 

 

 

(mW,

 

 

 

 

-THD

 

 

500

 

 

 

 

 

 

VDD

 

 

 

 

 

 

 

 

400

 

 

 

 

 

 

 

, I

 

 

 

 

 

 

 

DISS

300

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

200

 

 

 

 

 

 

 

 

100

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

0

 

 

 

 

OVDD (V)

 

 

 

 

 

 

 

 

 

 

toc27

 

 

PDISS (ANALOG)

 

 

MAX12557

 

 

 

 

 

 

 

 

 

 

IVDD

 

 

3.0

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

PDISS, IOVDD (DIGITAL)

vs. DIGITAL SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 175MHz)

 

80

CL

5pF

 

 

 

 

toc28

 

 

 

 

 

 

 

70

 

 

 

 

MAX12557

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

mA)

 

 

 

 

 

 

 

50

 

 

 

 

 

 

 

(mW,

 

PDISS (DIGITAL)

 

 

 

OVDD

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

, I

30

 

 

 

 

 

 

 

DISS

 

 

 

 

IOVDD

 

 

 

 

 

 

 

 

 

P

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

 

 

 

 

OVDD (V)

 

 

 

SNR, SINAD vs. CLOCK DUTY CYCLE

(fIN = 70MHz, AIN = -0.5dBFS)

 

72

SNR

toc29

 

90

 

 

 

 

 

 

MAX12557

 

 

 

70

 

 

85

 

 

 

 

 

(dB)

68

 

 

(dBc)

80

SINAD

 

 

 

SNR, SINAD

66

 

 

-THD, SFDR

75

64

 

 

70

 

 

 

 

 

62

 

 

 

65

 

 

 

SINGLE-ENDED CLOCK DRIVE

 

60

60

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

35

45

55

65

75

CLOCK DUTY CYCLE (%)

-THD, SFDR vs. CLOCK DUTY CYCLE

(fIN = 70MHz, AIN = -0.5dBFS)

SFDR

toc30

MAX12557

 

-THD

 

SINGLE-ENDED CLOCK DRIVE

25

35

45

55

65

75

 

 

CLOCK DUTY CYCLE (%)

 

 

10 ______________________________________________________________________________________

Image 10
Contents Applications FeaturesGeneral Description Ordering InformationAnalog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Conversion RateParameter Symbol Conditions MIN TYP MAX Units Internal Reference Refout Interchannel CharacteristicsVcom DIFFCLK/ Seclk = OV DD Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4DIFFCLK/SECLK = GND Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = OvddTiming Characteristics Figure Typical Operating CharacteristicsFFT Plot 32,768-POINT Data Record MAX12557 TWO-TONE IMD Plot 16,384-POINT Data RecordTHD, Sfdr vs. Clock Speed FIN = 70MHz, AIN = -0.5dBFSVs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFSGain Error vs. Temperature PIN Name Function Pin DescriptionSame side of the PC board D2B D0BD1B D3BRefout Detailed DescriptionShref RefinFunctional Diagram Analog Inputs and Input Track-and-Hold T/H Amplifier Reference ConfigurationsReference Mode Reference OutputClock Duty-Cycle Equalizer Clock Input and Clock Control LinesData-Valid Output System Timing RequirementsDIV4 DIV2 Function Output Codes vs. Input Voltage Power-Down Input Vrefp VrefnBinary-to-Gray and Gray-to-Binary Code Conversion Single-Ended AC-Coupled Input Signal Using Transformer CouplingApplications Information Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCsGrounding, Bypassing, and Board Layout MAX12557Parameter Definitions Overdrive Recovery Time Aperture DelayFull-Power Bandwidth Total Harmonic Distortion THDGain Matching Pin ConfigurationOffset Matching Package Information 68L QFN THIN.EPS