Maxim MAX12557 manual Grounding, Bypassing, and Board Layout

Page 24

 

Dual, 65Msps, 14-Bit, IF/Baseband ADC

 

 

MAX12557

3.3V

 

 

 

 

 

 

 

 

 

0.1F

 

3V

 

 

 

 

 

0.1F

2.2F

1

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20k

 

 

 

 

REF_P

VDD

 

 

MAX6029

1%

 

 

 

 

 

 

 

 

 

 

 

0.1F

 

REFOUT

 

 

(EUK30)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.1F

 

 

20k

 

 

 

10F

0.1F

 

 

 

 

 

 

 

 

 

 

1%

 

 

 

 

 

 

2

 

 

2.413V

 

MAX12557

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

47

 

 

REF_N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.1F

 

 

 

 

 

 

 

MAX4230

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.47F

 

3

 

330F

 

 

 

 

 

 

 

10F

 

 

 

 

 

 

 

 

 

6V

1.47k

6V

 

 

 

 

 

 

 

52.3k

 

 

 

COM_

 

 

 

 

 

 

 

 

 

REFIN

 

 

 

 

1%

 

 

 

0.1F

 

GND

 

 

 

 

 

 

 

1.647V

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

4

47

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX4230

 

 

 

3.3V

 

 

 

 

 

 

3

 

330F

 

 

 

 

 

 

 

 

10F

 

 

 

 

 

 

 

 

52.3k

6V

1.47k

6V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1%

 

 

 

 

0.1F

2.2F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0.880V

 

 

VDD

 

 

 

 

 

4

47

 

 

REF_P

 

 

 

 

 

 

 

 

 

 

 

 

20k

 

 

0.1F

 

REFOUT

 

 

 

 

MAX4230

 

 

 

 

 

 

 

1%

3

 

330F

 

 

 

0.1F

 

 

 

 

10F

 

10F

0.1F

 

 

 

 

 

 

 

 

 

 

 

 

6V

 

6V

 

 

 

 

 

 

1.47k

 

MAX12557

 

 

 

 

20k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1%

 

 

 

 

REF_N

 

 

 

 

 

 

 

 

 

0.1F

 

 

 

 

 

 

20k

 

 

 

 

 

 

 

 

 

 

1%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COM_

REFIN

 

 

 

 

 

 

 

 

0.1F

 

GND

 

 

 

 

 

 

 

 

 

 

 

Figure 13. External Unbuffered Reference Driving Multiple ADCs

ence, allowing REF_P, REF_N, and COM_ to be driven directly by a set of external reference sources.

Figure 13 uses a MAX6029 precision 3.000V bandgap reference as a common reference for multiple convert- ers. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47µF capacitor along this chain creates a 10Hz LP filter. Three MAX4230 amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and 0.880V to the MAX12557 REF_P, REF_N, and COM_ reference inputs. The feedback around the MAX4230 op amps provides additional 10Hz LP filtering. Reference volt- ages 2.413V and 0.880V set the full-scale analog input

range for the converter to ±1.022V (±[VREF_P - VREF_N] x 2/3).

Note that one single power supply for all active circuit components removes any concern regarding power- supply sequencing when powering up or down.

Grounding, Bypassing, and Board Layout

The MAX12557 requires high-speed board layout design techniques. Refer to the MAX12557 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, prefer- ably on the same side as the ADC, using surface-

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Contents Features General DescriptionApplications Ordering InformationParameter Symbol Conditions MIN TYP MAX Units DC Accuracy Dynamic Characteristics differential inputsAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom Clock Inputs CLKP, Clkn DIFFCLK/ Seclk = GND, Clkn = GNDDIFFCLK/ Seclk = OV DD Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4Power Requirements D0A-D13A, DoraDIFFCLK/SECLK = GND DIFFCLK/SECLK = OvddTypical Operating Characteristics Timing Characteristics FigureFFT Plot 32,768-POINT Data Record MAX12557 TWO-TONE IMD Plot 16,384-POINT Data RecordTHD, Sfdr vs. Clock Speed FIN = 70MHz, AIN = -0.5dBFSFCLK = 65.00352MHz, fIN = 175MHz PDISS, Iovdd DigitalVs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFSGain Error vs. Temperature Pin Description PIN Name FunctionSame side of the PC board D0B D1BD2B D3BDetailed Description ShrefRefout RefinFunctional Diagram Reference Configurations Reference ModeAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Duty-Cycle Equalizer Clock Input and Clock Control LinesSystem Timing Requirements Data-Valid OutputDIV4 DIV2 Function Output Codes vs. Input Voltage Power-Down Input Vrefp VrefnBinary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCsGrounding, Bypassing, and Board Layout MAX12557Parameter Definitions Aperture Delay Full-Power BandwidthOverdrive Recovery Time Total Harmonic Distortion THDPin Configuration Gain MatchingOffset Matching Package Information 68L QFN THIN.EPS