Maxim MAX12557 manual Applications Information, Using Transformer Coupling

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Dual, 65Msps, 14-Bit, IF/Baseband ADC

MAX12557

Applications Information

Using Transformer Coupling

In general, the MAX12557 provides better SFDR and THD with fully differential input signals than single- ended input drive, especially for input frequencies above 125MHz. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode.

An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12557 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the

 

 

 

24.9

 

 

 

IN_P

 

 

 

5.6pF

 

0.1F

 

MAX12557

VIN

1

6

T1

 

 

 

5

2

COM_

 

N.C.

 

 

3

4

0.1F

 

 

 

MINICIRCUITS

 

 

TT1-6

 

 

 

OR

 

24.9

 

T1-1T

 

IN_N

 

 

 

5.6pF

overall distortion. The configuration of Figure 9 is good for frequencies up to Nyquist (fCLK / 2).

The circuit of Figure 10 converts a single-ended input signal to fully differential just as Figure 9. However, Figure 10 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. A set of 75and 113termination resistors provide an equivalent 50termination to the signal source. The second set of termination resistors connects to COM_ providing the correct input common-mode voltage. Two 0resistors in series with the analog inputs allow high IF input fre- quencies. These 0resistors can be replaced with low- value resistors to limit the input bandwidth.

Single-Ended AC-Coupled Input Signal

Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.

VIN

0.1F

0

 

 

 

MAX4108

 

IN_P

 

5.6pF

 

 

100

 

24.9

 

 

MAX12557

 

 

COM_

 

 

0.1F

100

 

24.9

 

 

IN_N

 

 

5.6pF

Figure 9. Transformer-Coupled Input Drive for Input Frequencies

Figure 11. Single-Ended, AC-Coupled Input Drive

Up to Nyquist

 

 

 

 

 

 

 

 

0*

 

0.1F

 

 

 

 

 

5.6pF

 

1

6

 

1

6

 

VIN

75

 

113

T1

 

T2

 

 

 

 

 

1%

 

 

 

0.5%

 

5

2

N.C.

5

2

N.C.

 

 

N.C.

 

N.C.

 

 

 

 

 

75

 

 

 

0.1F

 

3

4

3

4

 

113

 

MINICIRCUITS

1%

MINICIRCUITS

 

0.5%

 

 

 

0*

 

ADT1-1WT

 

ADT1-1WT

 

 

 

 

 

 

 

 

*0RESISTORS CAN BE REPLACED WITH

5.6pF

 

 

 

 

LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.

IN_P

MAX12557

COM_

IN_N

Figure 10. Transformer-Coupled Input Drive for Input Frequencies beyond Nyquist

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Contents Applications FeaturesGeneral Description Ordering InformationAnalog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Conversion RateParameter Symbol Conditions MIN TYP MAX Units Internal Reference Refout Interchannel CharacteristicsVcom DIFFCLK/ Seclk = OV DD Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4DIFFCLK/SECLK = GND Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = OvddTiming Characteristics Figure Typical Operating CharacteristicsFFT Plot 32,768-POINT Data Record MAX12557 TWO-TONE IMD Plot 16,384-POINT Data RecordTHD, Sfdr vs. Clock Speed FIN = 70MHz, AIN = -0.5dBFSVs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFSGain Error vs. Temperature PIN Name Function Pin DescriptionSame side of the PC board D2B D0BD1B D3BRefout Detailed DescriptionShref RefinFunctional Diagram Analog Inputs and Input Track-and-Hold T/H Amplifier Reference ConfigurationsReference Mode Reference OutputClock Duty-Cycle Equalizer Clock Input and Clock Control LinesData-Valid Output System Timing RequirementsDIV4 DIV2 Function Output Codes vs. Input Voltage Power-Down Input Vrefp VrefnBinary-to-Gray and Gray-to-Binary Code Conversion Single-Ended AC-Coupled Input Signal Using Transformer CouplingApplications Information Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCsGrounding, Bypassing, and Board Layout MAX12557Parameter Definitions Overdrive Recovery Time Aperture DelayFull-Power Bandwidth Total Harmonic Distortion THDGain Matching Pin ConfigurationOffset Matching Package Information 68L QFN THIN.EPS