Maxim MAX12557 manual Gain Error vs. Temperature

Page 11

Dual, 65Msps, 14-Bit, IF/Baseband ADC

Typical Operating Characteristics (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL ≈ 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

SNR, SINAD vs. TEMPERATURE (fIN = 175MHz, AIN = -0.5dBFS)

	76					toc31
			SNR			toc31
	74		SNR			MAX12557
	74
	72
	72
(dB)	70
SINAD	68		SINAD
SNR,	66
	64
	62
	60
	-40	-15	10	35	60	85
			TEMPERATURE (°C)

-THD, SFDR vs. TEMPERATURE (fIN = 175MHz, AIN = -0.5dBFS)

	90					toc32
						toc32
	85					MAX12557
						MAX12557
SFDR (dBc)	80				SFDR
	80
	75
-THD,	70			-THD
	70
	65
	60
	-40	-15	10	35	60	85

TEMPERATURE (°C)

MAX12557

GAIN ERROR vs. TEMPERATURE

OFFSET ERROR vs. TEMPERATURE

	3					toc33
						toc33
	2					MAX12557
(%FSR)ERRORGAIN	1					(%FSR)ERROROFFSET
	1
	0
	-1
	-2
	-3
	-40	-15	10	35	60	85

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

MAX12557 toc34

-40

-15

10

35

60

85

TEMPERATURE (°C)

TEMPERATURE (°C)

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Image 11

Contents Ordering Information FeaturesGeneral Description ApplicationsConversion Rate Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Analog Input INAP, INAN, INBP, InbnParameter Symbol Conditions MIN TYP MAX Units Vcom Interchannel CharacteristicsInternal Reference Refout Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND DIFFCLK/ Seclk = OV DDDIFFCLK/SECLK = Ovdd Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = GNDFFT Plot 32,768-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure TWO-TONE IMD Plot 16,384-POINT Data Record MAX12557FIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock SpeedSNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital Vs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHzGain Error vs. Temperature Same side of the PC board Pin DescriptionPIN Name Function D3B D0BD1B D2BRefin Detailed DescriptionShref RefoutFunctional Diagram Reference Output Reference ConfigurationsReference Mode Analog Inputs and Input Track-and-Hold T/H AmplifierClock Input and Clock Control Lines Clock Duty-Cycle EqualizerDIV4 DIV2 Function System Timing RequirementsData-Valid Output Output Codes vs. Input Voltage Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Applications Information Using Transformer CouplingSingle-Ended AC-Coupled Input Signal Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12557 Grounding, Bypassing, and Board LayoutParameter Definitions Total Harmonic Distortion THD Aperture DelayFull-Power Bandwidth Overdrive Recovery TimeOffset Matching Pin ConfigurationGain Matching 68L QFN THIN.EPS Package Information