Maxim MAX12557 manual Pin Configuration, Gain Matching, Offset Matching

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Dual, 65Msps, 14-Bit, IF/Baseband ADC

Gain Matching

Gain matching is a figure of merit that indicates how well the gains between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in gain is report- ed (typically in dB) as gain matching.

Offset Matching

Like gain matching, offset matching is a figure of merit that indicates how well the offsets between the two chan- nels are matched to each other. The same input signal is applied to both channels and the maximum deviation in offset is reported (typically in %FSR) as offset matching.

Pin Configuration

TOP VIEW		REFOUT	SHREF
	REFIN			PD	G/T	DD	DD	DD	DD	DORA	D13A	D12A	D11A	D10A	D9A	D8A	D7A
	REFIN			PD	G/T	V	V	V	OV	DORA	D13A	D12A	D11A	D10A	D9A	D8A	D7A
	68	67	66	65	64	63	62	61	60	59	58	57	56	55	54	53	52
GND	1																51	D6A
INAP	2																50	D5A
INAN	3																49	D4A
GND	4																48	D3A
GND	5																47	D2A
COMA	6																46	D1A
REFAP	7																45	D0A
REFAN	8																44	DAV
GND	9							MAX12557									43	OVDD
REFBN	10							MAX12557									42	DORB
REFBN	10																42	DORB
REFBP	11																41	D13B
COMB	12																40	D12B
GND	13																39	D11B
GND	14																38	D10B
INBN	15		EXPOSED PADDLE (GND)														37	D9B
INBP	16		EXPOSED PADDLE (GND)															D8B
INBP	16																36	D8B
GND	17																35	D7B
	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32	33	34
	DIFFCLK/SECLK	CLKN	CLKP	DIV2	DIV4	DD	DD	DD	DD	DD	D0B	D1B	D2B	D3B	D4B	D5B	D6B
						DD	DD	V	V	OV	D0B
						V	V	THIN QFN
						V	V

MAX12557

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Contents Ordering Information FeaturesGeneral Description ApplicationsConversion Rate Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Analog Input INAP, INAN, INBP, InbnParameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND DIFFCLK/ Seclk = OV DDDIFFCLK/SECLK = Ovdd Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = GNDTypical Operating Characteristics Timing Characteristics FigureFFT Plot 32,768-POINT Data Record TWO-TONE IMD Plot 16,384-POINT Data Record MAX12557FIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock SpeedSNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital Vs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHzGain Error vs. Temperature Pin Description PIN Name FunctionSame side of the PC board D3B D0BD1B D2BRefin Detailed DescriptionShref RefoutFunctional Diagram Reference Output Reference ConfigurationsReference Mode Analog Inputs and Input Track-and-Hold T/H AmplifierClock Input and Clock Control Lines Clock Duty-Cycle EqualizerSystem Timing Requirements Data-Valid OutputDIV4 DIV2 Function Output Codes vs. Input Voltage Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12557 Grounding, Bypassing, and Board LayoutParameter Definitions Total Harmonic Distortion THD Aperture DelayFull-Power Bandwidth Overdrive Recovery TimePin Configuration Gain MatchingOffset Matching 68L QFN THIN.EPS Package Information