Maxim MAX12557 D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B, D8B, D9B, Dorb, D0A, D1A, D2A, D3A, D4A

Page 13

Dual, 65Msps, 14-Bit, IF/Baseband ADC

 

 

 

Pin Description (continued)

 

 

 

 

 

PIN

NAME

 

FUNCTION

 

 

 

 

 

28

D0B

Channel B CMOS Digital Output, Bit 0 (LSB)

 

 

 

 

 

29

D1B

Channel B CMOS Digital Output, Bit 1

30

D2B

Channel B CMOS Digital Output, Bit 2

 

 

 

 

 

31

D3B

Channel B CMOS Digital Output, Bit 3

 

 

 

 

 

32

D4B

Channel B CMOS Digital Output, Bit 4

 

 

 

 

 

33

D5B

Channel B CMOS Digital Output, Bit 5

 

 

 

 

 

34

D6B

Channel B CMOS Digital Output, Bit 6

35

D7B

Channel B CMOS Digital Output, Bit 7

 

 

 

 

 

36

D8B

Channel B CMOS Digital Output, Bit 8

 

 

 

 

 

37

D9B

Channel B CMOS Digital Output, Bit 9

 

 

 

 

 

38

D10B

Channel B CMOS Digital Output, Bit 10

39

D11B

Channel B CMOS Digital Output, Bit 11

 

 

 

 

 

40

D12B

Channel B CMOS Digital Output, Bit 12

 

 

 

 

 

41

D13B

Channel B CMOS Digital Output, Bit 13 (MSB)

 

 

 

 

 

 

 

Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog

42

DORB

input voltage is out of range.

DORB = 1: Digital outputs exceed full-scale range.

 

 

 

 

DORB = 0: Digital outputs are within full-scale range.

 

 

 

 

 

44

DAV

Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs.

The MAX12557 evaluation kit utilizes DAV to latch data into any external back-end digital logic.

 

 

45

D0A

Channel A CMOS Digital Output, Bit 0 (LSB)

 

 

 

 

 

46

D1A

Channel A CMOS Digital Output, Bit 1

 

 

 

 

 

47

D2A

Channel A CMOS Digital Output, Bit 2

48

D3A

Channel A CMOS Digital Output, Bit 3

 

 

 

 

 

49

D4A

Channel A CMOS Digital Output, Bit 4

 

 

 

 

 

50

D5A

Channel A CMOS Digital Output, Bit 5

51

D6A

Channel A CMOS Digital Output, Bit 6

 

 

 

 

 

52

D7A

Channel A CMOS Digital Output, Bit 7

 

 

 

 

 

53

D8A

Channel A CMOS Digital Output, Bit 8

54

D9A

Channel A CMOS Digital Output, Bit 9

 

 

 

 

 

55

D10A

Channel A CMOS Digital Output, Bit 10

 

 

 

 

 

56

D11A

Channel A CMOS Digital Output, Bit 11

57

D12A

Channel A CMOS Digital Output, Bit 12

 

 

 

 

 

58

D13A

Channel A CMOS Digital Output, Bit 13 (MSB)

 

 

 

 

 

 

 

Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog

59

DORA

input voltage is out of range.

DORA = 1: Digital outputs exceed full-scale range.

 

 

 

 

DORA = 0: Digital outputs are within full-scale range.

 

 

Output Format Select Digital Input.

64

G/T

G/T = GND: Two’s-complement output format selected.

 

 

G/T = OVDD: Gray-code output format selected.

MAX12557

______________________________________________________________________________________ 13

Image 13
Contents General Description FeaturesApplications Ordering InformationDynamic Characteristics differential inputs Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Internal Reference Refout Interchannel CharacteristicsVcom DIFFCLK/ Seclk = GND, Clkn = GND Clock Inputs CLKP, ClknDIFFCLK/ Seclk = OV DD Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4D0A-D13A, Dora Power RequirementsDIFFCLK/SECLK = GND DIFFCLK/SECLK = OvddTiming Characteristics Figure Typical Operating CharacteristicsFFT Plot 32,768-POINT Data Record TWO-TONE IMD Plot 16,384-POINT Data Record MAX12557FIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock SpeedPDISS, Iovdd Digital FCLK = 65.00352MHz, fIN = 175MHzVs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFSGain Error vs. Temperature PIN Name Function Pin DescriptionSame side of the PC board D1B D0BD2B D3BShref Detailed DescriptionRefout RefinFunctional Diagram Reference Mode Reference ConfigurationsAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Input and Clock Control Lines Clock Duty-Cycle EqualizerData-Valid Output System Timing RequirementsDIV4 DIV2 Function Output Codes vs. Input Voltage Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Single-Ended AC-Coupled Input Signal Using Transformer CouplingApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12557 Grounding, Bypassing, and Board LayoutParameter Definitions Full-Power Bandwidth Aperture DelayOverdrive Recovery Time Total Harmonic Distortion THDGain Matching Pin ConfigurationOffset Matching 68L QFN THIN.EPS Package Information