Maxim MAX12557 manual Buffered External Reference Drives Multiple ADCs

Page 23

Dual, 65Msps, 14-Bit, IF/Baseband ADC

3.3V

0.1∝F2.2∝F

MAX12557

0.1∝F1

5

MAX6029

(EUK21)

2

16.2kΩ

1∝F

3

4

									0.1∝F	2.048V
5									0.1∝F	300∝F
									47Ω




			1							6V

MAX4230

2

1.47kΩ

VDD

REFINREF_P

MAX12557

REF_N

REFOUTCOM_

0.1∝F

10∝F		0.1∝F

0.1∝F

0.1∝F

GND

0.1∝F

NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING UP TO 15mA AND SINKING UP TO 30mA OF OUTPUT CURRENT.

0.1∝F

0.1∝F

VDD

REFINREF_P

MAX12557

REF_N

REFOUTCOM_

GND

3.3V

2.2∝F

0.1∝F

10∝F		0.1∝F

0.1∝F

0.1∝F

Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference

Buffered External Reference Drives Multiple ADCs

The buffered external reference mode allows for more control over the MAX12557 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50MΩ.

Figure 12 shows the MAX6029 precision 2.048V bandgap reference used as a common reference for multiple con- verters. The 2.048V output of the MAX6029 passes through a single-pole 10Hz LP filter to the MAX4230.

The MAX4250 buffers the 2.048V reference and pro- vides additional 10Hz LP filtering before its output is applied to the REFIN input of the MAX12557.

Unbuffered External Reference Drives Multiple ADCs

The unbuffered external reference mode allows for pre- cise control over the MAX12557 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal refer-

______________________________________________________________________________________ 23

Image 23

Contents Ordering Information FeaturesGeneral Description ApplicationsConversion Rate Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Analog Input INAP, INAN, INBP, InbnParameter Symbol Conditions MIN TYP MAX Units Vcom Interchannel CharacteristicsInternal Reference Refout Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4 Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND DIFFCLK/ Seclk = OV DDDIFFCLK/SECLK = Ovdd Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = GNDFFT Plot 32,768-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure TWO-TONE IMD Plot 16,384-POINT Data Record MAX12557FIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock SpeedSNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFS FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital Vs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHzGain Error vs. Temperature Same side of the PC board Pin DescriptionPIN Name Function D3B D0BD1B D2BRefin Detailed DescriptionShref RefoutFunctional Diagram Reference Output Reference ConfigurationsReference Mode Analog Inputs and Input Track-and-Hold T/H AmplifierClock Input and Clock Control Lines Clock Duty-Cycle EqualizerDIV4 DIV2 Function System Timing RequirementsData-Valid Output Output Codes vs. Input Voltage Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Applications Information Using Transformer CouplingSingle-Ended AC-Coupled Input Signal Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12557 Grounding, Bypassing, and Board LayoutParameter Definitions Total Harmonic Distortion THD Aperture DelayFull-Power Bandwidth Overdrive Recovery TimeOffset Matching Pin ConfigurationGain Matching 68L QFN THIN.EPS Package Information