Maxim MAX12557 manual Parameter Symbol Conditions MIN TYP MAX Units DC Accuracy, Conversion Rate

Page 2

Dual, 65Msps, 14-Bit, IF/Baseband ADC

MAX12557

ABSOLUTE MAXIMUM RATINGS

VDD to GND

-0.3V to +3.6V

OVDD to GND

-0.3V to the lower of (VDD + 0.3V) and +3.6V

INAP, INAN to GND ...

-0.3V to the lower of (VDD + 0.3V) and +3.6V

INBP, INBN to GND ...

-0.3V to the lower of (VDD + 0.3V) and +3.6V

CLKP, CLKN........................to

-0.3V to the lower of (VDD + 0.3V) and +3.6V

GND

REFIN, REFOUT

-0.3V to the lower of (VDD + 0.3V) and +3.6V

to GND

REFAP, REFAN,

-0.3V to the lower of (VDD + 0.3V) and +3.6V

COMA to GND

REFBP, REFBN,

-0.3V to the lower of (VDD + 0.3V) and +3.6V

COMB to GND

DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,

 

DIV4 to GND

.........-0.3V to the lower of (VDD + 0.3V) and +3.6V

D0A–D13A,D0B–D13B, ..............................DAV,

-0.3V to (OVDD + 0.3V)

DORA, DORB to GND

Continuous Power Dissipation (TA = +70°C)

 

68-Pin Thin QFN 10mm x 10mm x 0.8mm

 

(derate 70mW/°C above +70°C)

4000mW

Operating Temperature Range

-40°C to +85°C

Junction Temperature

+150°C

Storage Temperature Range

-65°C to +150°C

Lead Temperature (soldering 10s)

+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, VIN = -0.5dBFS (differen- tial), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 65MHz, TA = -40°C to

+85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

DC ACCURACY

 

 

 

 

 

 

 

 

 

 

 

 

 

Resolution

 

 

14

 

 

Bits

Integral Nonlinearity

INL

fIN = 3MHz

 

±2.1

 

LSB

Differential Nonlinearity

DNL

fIN = 3MHz, no missing codes over

-1.0

±0.6

+1.3

LSB

temperature (Note 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset Error

 

 

 

±0.1

±0.9

%FSR

 

 

 

 

 

 

 

Gain Error

 

 

 

±0.5

±5.0

%FSR

 

 

 

 

 

 

 

ANALOG INPUT (INAP, INAN, INBP, INBN)

 

 

 

 

 

 

 

 

 

 

 

 

Differential Input Voltage Range

VDIFF

Differential or single-ended inputs

 

±1.024

 

V

Common-Mode Input Voltage

 

 

 

VDD / 2

 

V

Analog Input Resistance

RIN

Each input, Figure 3

 

3.4

 

k

 

CPAR

Fixed capacitance to ground,

 

2

 

 

 

each input, Figure 3

 

 

 

Analog Input Capacitance

 

 

 

 

pF

 

 

 

 

 

CSAMPLE

Switched capacitance,

 

4.5

 

 

 

 

 

 

each input, Figure 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONVERSION RATE

 

 

 

 

 

 

Maximum Clock Frequency

fCLK

 

65

 

 

MHz

Minimum Clock Frequency

 

 

 

 

5

MHz

Data Latency

 

Figure 5

 

8

 

Clock

 

 

 

Cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

DYNAMIC CHARACTERISTICS (differential inputs)

 

 

 

 

 

 

 

 

 

 

 

Small-Signal Noise Floor

SSNF

Input at -35dBFS

74.5

76

 

dBFS

 

 

fIN = 3MHz at -0.5dBFS

72.5

75

 

 

Signal-to-Noise Ratio

SNR

fIN = 32.5MHz at -0.5dBFS

 

74.5

 

dB

fIN = 70MHz at -0.5dBFS

 

74.1

 

 

 

 

 

 

 

 

fIN = 175MHz at -0.5dBFS

70.4

72.5

 

 

2 _______________________________________________________________________________________

Image 2
Contents Applications FeaturesGeneral Description Ordering InformationAnalog Input INAP, INAN, INBP, Inbn Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyDynamic Characteristics differential inputs Conversion RateParameter Symbol Conditions MIN TYP MAX Units Vcom Interchannel CharacteristicsInternal Reference Refout DIFFCLK/ Seclk = OV DD Clock Inputs CLKP, ClknDIFFCLK/ Seclk = GND, Clkn = GND Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4DIFFCLK/SECLK = GND Power RequirementsD0A-D13A, Dora DIFFCLK/SECLK = OvddFFT Plot 32,768-POINT Data Record Typical Operating CharacteristicsTiming Characteristics Figure MAX12557 TWO-TONE IMD Plot 16,384-POINT Data RecordTHD, Sfdr vs. Clock Speed FIN = 70MHz, AIN = -0.5dBFSVs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz FCLK = 65.00352MHz, fIN = 175MHzPDISS, Iovdd Digital SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFSGain Error vs. Temperature Same side of the PC board Pin DescriptionPIN Name Function D2B D0BD1B D3BRefout Detailed DescriptionShref RefinFunctional Diagram Analog Inputs and Input Track-and-Hold T/H Amplifier Reference ConfigurationsReference Mode Reference OutputClock Duty-Cycle Equalizer Clock Input and Clock Control LinesDIV4 DIV2 Function System Timing RequirementsData-Valid Output Output Codes vs. Input Voltage Power-Down Input Vrefp VrefnBinary-to-Gray and Gray-to-Binary Code Conversion Applications Information Using Transformer CouplingSingle-Ended AC-Coupled Input Signal Buffered External Reference Drives Multiple ADCs Unbuffered External Reference Drives Multiple ADCsGrounding, Bypassing, and Board Layout MAX12557Parameter Definitions Overdrive Recovery Time Aperture DelayFull-Power Bandwidth Total Harmonic Distortion THDOffset Matching Pin ConfigurationGain Matching Package Information 68L QFN THIN.EPS