Maxim MAX12557 manual Binary-to-Gray and Gray-to-Binary Code Conversion

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+ GRAYX

Dual, 65Msps, 14-Bit, IF/Baseband ADC

BINARY-TO-GRAY CODE CONVERSION

1)THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT.

D13

 

D11

 

 

 

D7

 

 

 

D3

 

 

D0

BIT POSITION

0

1

1

0

1

1

0

1

0

0

1

1

0

0

BINARY

0

 

 

 

 

 

 

 

 

 

 

 

 

 

GRAY CODE

2)SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

GRAYX = BINARYX + BINARYX + 1

WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH

TABLE BELOW) AND X IS THE BIT POSITION:

GRAY12 = BINARY12 + BINARY13

GRAY12 = 1 + 0

GRAY12 = 1

D13

 

D11

D7

D3

D0

BIT POSITION

0

+ 1

1 0 1 1

0 1 0 0

1

1 0 0

BINARY

0

1

 

 

 

 

GRAY CODE

3)REPEAT STEP 2 UNTIL COMPLETE: GRAY11 = BINARY11 + BINARY12 GRAY11 = 1 + 1

GRAY11 = 0

D13

 

 

 

D11

 

D7

 

 

 

D3

 

 

D0

BIT POSITION

0

1

+

1

0

1

1

0 1

0

0

 

1

1

0

0

BINARY

0

1

 

0

 

 

 

 

 

 

 

 

 

 

 

GRAY CODE

4) THE FINAL GRAY-CODE CONVERSION IS:

 

 

 

 

 

 

D13

 

D11

 

 

 

D7

 

 

 

D3

 

 

D0

BIT POSITION

 

 

 

 

 

 

 

 

 

 

0

 

1

1

0

1

1

0

1

0

0

1

1

0

0

BINARY

0

 

1

0

1

1

0

1

1

1

0

1

0

1

0

GRAY CODE

GRAY-TO-BINARY CODE CONVERSION

1)THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT.

D13

 

D11

 

 

 

D7

 

 

 

D3

 

 

D0

0

1

0

1

1

0

1

1

1

0

1

0

1

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

2)SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION:

BINARYX = BINARYX+1

WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION:

BINARY12 = BINARY13 + GRAY12

BINARY12 = 0 + 1

BINARY12 = 1

D13

 

D11

 

 

 

D7

 

 

 

D3

 

 

D0

0

1

0

1

1

0

1

1

1

0

1

0

1

0

 

+

 

 

 

 

 

 

 

 

 

 

 

 

01

3)REPEAT STEP 2 UNTIL COMPLETE:

BINARY11 = BINARY12 + GRAY11

BINARY11 = 1 + 0

BINARY11 = 1

D13

 

 

D11

 

D7

 

 

 

D3

 

 

D0

0

1

0

1

1

0

1

1

1

0

1

0

1

0

 

 

+

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

 

 

 

 

 

 

 

 

 

 

4) THE FINAL BINARY CONVERSION IS:

 

 

 

 

 

 

D13

 

D11

 

 

 

D7

 

 

 

D3

 

 

D0

0

1

0

1

1

0

1

1

1

0

1

0

1

0

0

1

1

0

1

1

0

1

0

0

1

1

0

0

BIT POSITION GRAY CODE

BINARY

BIT POSITION GRAY CODE

BINARY

BIT POSITION

GRAY CODE

BINARY

BIT POSITION GRAY CODE

BINARY

MAX12557

 

 

EXCLUSIVE OR TRUTH TABLE

FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY

A

B

Y = A + B

CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT

 

 

 

FORMAT OF THE MAX12557 IS TWO'S-COMPLEMENT BINARY,

0

0

0

HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE

0

1

1

MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT.

1

0

1

 

 

1

1

0

Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion

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Contents General Description FeaturesApplications Ordering InformationDynamic Characteristics differential inputs Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom DIFFCLK/ Seclk = GND, Clkn = GND Clock Inputs CLKP, ClknDIFFCLK/ Seclk = OV DD Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4D0A-D13A, Dora Power RequirementsDIFFCLK/SECLK = GND DIFFCLK/SECLK = OvddTypical Operating Characteristics Timing Characteristics FigureFFT Plot 32,768-POINT Data Record TWO-TONE IMD Plot 16,384-POINT Data Record MAX12557FIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock SpeedPDISS, Iovdd Digital FCLK = 65.00352MHz, fIN = 175MHzVs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFSGain Error vs. Temperature Pin Description PIN Name FunctionSame side of the PC board D1B D0BD2B D3BShref Detailed DescriptionRefout RefinFunctional Diagram Reference Mode Reference ConfigurationsAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Input and Clock Control Lines Clock Duty-Cycle EqualizerSystem Timing Requirements Data-Valid OutputDIV4 DIV2 Function Output Codes vs. Input Voltage Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12557 Grounding, Bypassing, and Board LayoutParameter Definitions Full-Power Bandwidth Aperture DelayOverdrive Recovery Time Total Harmonic Distortion THDPin Configuration Gain MatchingOffset Matching 68L QFN THIN.EPS Package Information