Maxim MAX12557 manual THD, Sfdr vs. Clock Speed, FIN = 70MHz, AIN = -0.5dBFS

Page 9

Dual, 65Msps, 14-Bit, IF/Baseband ADC

Typical Operating Characteristics (continued)

(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, VIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)

SNR, SINAD vs. ANALOG INPUT AMPLITUDE

-THD, SFDR vs. ANALOG INPUT AMPLITUDE

(fCLK = 65.00352MHz, fIN = 175MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

SNR, SINAD vs. CLOCK SPEED (fIN = 70MHz, AIN = -0.5dBFS)

 

80

 

toc13

 

95

 

SNR

 

 

 

MAX12557

 

 

 

70

 

 

85

 

 

 

 

 

(dB)

60

SINAD

 

(dBc)

75

 

 

 

 

SNR, SINAD

50

 

 

-THD, SFDR

65

40

 

 

55

 

 

 

 

 

30

 

 

 

45

 

20

 

 

 

35

 

-55 -50 -45 -40 -35 -30 -25 -20 -15 -10

-5

0

 

 

 

 

toc14

 

80

 

 

 

 

SFDR

 

MAX12557

 

76

 

 

 

 

 

 

(dB)

72

 

 

 

SINAD

-THD

 

 

 

 

 

 

SNR,

68

 

 

 

 

 

 

 

 

64

-55 -50 -45 -40 -35 -30 -25 -20 -15 -10

-5

0

 

60

 

 

 

 

 

 

 

SNR

 

 

MAX12557 toc15

 

 

 

 

 

 

SINAD

 

 

20

25

30

35

40

45

50

55

60

65

MAX12557

AIN (dBFS)

AIN (dBFS)

fCLK (MHz)

-THD, SFDR vs. CLOCK SPEED

SNR, SINAD vs. CLOCK SPEED

-THD, SFDR vs. CLOCK SPEED

(fIN = 70MHz, AIN = -0.5dBFS)

(fIN = 175MHz, AIN = -0.5dBFS)

(fIN = 175MHz, AIN = -0.5dBFS)

 

90

SFDR

 

 

 

 

 

 

toc16

 

80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX12557

 

 

 

85

 

 

 

 

 

 

 

 

 

76

(dBc)

80

 

 

 

-THD

 

 

 

 

(dB)

72

 

 

 

 

 

 

 

 

 

 

SFDR

 

 

 

 

 

 

 

 

 

 

SINAD

75

 

 

 

 

 

 

 

 

 

 

-THD,

70

 

 

 

 

 

 

 

 

 

SNR,

68

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

 

 

 

 

 

 

 

 

 

 

64

 

 

 

 

 

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

 

 

 

60

 

20

25

30

35

40

45

50

55

60

65

 

 

 

 

 

 

 

fCLK (MHz)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

toc17

90

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SNR

 

 

MAX12557

85

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SFDR (dBc)

80

 

 

 

 

 

SINAD

 

 

75

 

 

 

 

 

 

 

-THD,

 

 

 

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

20

25

30

35

40

45

50

55

60

65

60

 

 

 

 

 

fCLK (MHz)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

toc18

 

 

 

 

 

SFDR

 

 

 

MAX12557

 

 

 

 

 

 

 

 

 

 

 

 

-THD

 

 

 

 

 

20

25

30

35

40

45

50

55

60

65

 

 

 

 

fCLK (MHz)

 

 

 

 

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

-THD, SFDR vs. ANALOG SUPPLY VOLTAGE

SNR, SINAD vs. ANALOG SUPPLY VOLTAGE

(fCLK = 65.00352MHz, fIN = 70MHz)

(fCLK = 65.00352MHz, fIN = 70MHz)

(fCLK = 65.00352MHz, fIN = 175MHz)

 

80

 

 

 

 

 

toc19

 

95

 

 

 

 

 

 

 

 

 

 

76

 

SNR

 

 

 

MAX12557

 

90

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SINAD (dB)

 

 

 

 

 

 

 

SFDR (dBc)

85

72

 

SINAD

 

 

 

80

 

 

 

 

 

 

 

 

 

 

 

 

 

SNR,

68

 

 

 

 

 

 

THD,

75

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

 

 

 

 

 

 

 

 

 

 

70

 

64

 

 

 

 

 

 

 

65

 

 

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

60

 

3.0

3.1

3.2

3.3

3.4

3.5

3.6

 

 

 

 

 

 

 

 

toc20

 

75

 

 

 

 

 

 

 

 

 

 

 

 

SFDR

 

MAX12557

 

 

 

 

 

 

 

 

 

72

 

 

 

 

 

 

 

(dB)

69

 

 

 

-THD

 

 

 

SINAD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SNR,

66

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

 

 

 

 

 

 

 

 

60

3.0

3.1

3.2

3.3

3.4

3.5

3.6

 

 

 

 

SNR

 

 

 

toc21

 

 

 

 

 

MAX12557

 

 

 

 

 

 

 

 

 

SINAD

 

 

 

3.0

3.1

3.2

3.3

3.4

3.5

3.6

VDD (V)

VDD (V)

VDD (V)

_______________________________________________________________________________________ 9

Image 9
Contents General Description FeaturesApplications Ordering InformationDynamic Characteristics differential inputs Parameter Symbol Conditions MIN TYP MAX Units DC AccuracyAnalog Input INAP, INAN, INBP, Inbn Conversion RateParameter Symbol Conditions MIN TYP MAX Units Interchannel Characteristics Internal Reference RefoutVcom DIFFCLK/ Seclk = GND, Clkn = GND Clock Inputs CLKP, ClknDIFFCLK/ Seclk = OV DD Digital Inputs DIFFCLK/ SECLK, G/ T, PD, DIV2, DIV4D0A-D13A, Dora Power RequirementsDIFFCLK/SECLK = GND DIFFCLK/SECLK = OvddTypical Operating Characteristics Timing Characteristics FigureFFT Plot 32,768-POINT Data Record TWO-TONE IMD Plot 16,384-POINT Data Record MAX12557FIN = 70MHz, AIN = -0.5dBFS THD, Sfdr vs. Clock SpeedPDISS, Iovdd Digital FCLK = 65.00352MHz, fIN = 175MHzVs. Digital Supply Voltage FCLK = 65.00352MHz, fIN = 175MHz SNR, Sinad vs. Clock Duty Cycle FIN = 70MHz, AIN = -0.5dBFSGain Error vs. Temperature Pin Description PIN Name FunctionSame side of the PC board D1B D0BD2B D3BShref Detailed DescriptionRefout RefinFunctional Diagram Reference Mode Reference ConfigurationsAnalog Inputs and Input Track-and-Hold T/H Amplifier Reference OutputClock Input and Clock Control Lines Clock Duty-Cycle EqualizerSystem Timing Requirements Data-Valid OutputDIV4 DIV2 Function Output Codes vs. Input Voltage Vrefp Vrefn Power-Down InputBinary-to-Gray and Gray-to-Binary Code Conversion Using Transformer Coupling Single-Ended AC-Coupled Input SignalApplications Information Unbuffered External Reference Drives Multiple ADCs Buffered External Reference Drives Multiple ADCsMAX12557 Grounding, Bypassing, and Board LayoutParameter Definitions Full-Power Bandwidth Aperture DelayOverdrive Recovery Time Total Harmonic Distortion THDPin Configuration Gain MatchingOffset Matching 68L QFN THIN.EPS Package Information