Texas Instruments TMS320DM644x manual Supported Use Case Statement

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Peripheral Architecture

 

 

 

Figure 1. MMC/SD Card Controller Block Diagram

ARM CPU

 

 

 

 

MMC/SD

 

 

interface

DMA requests

Status

CLK

and

 

divider

Interrupts

registers

 

 

 

FIFO

1.4Supported Use Case Statement

The MMC/SD card controller supports the following user cases:

∙MMC/SD card identification

∙MMC/SD single-block read using CPU

∙MMC/SD single-block read using EDMA

∙MMC/SD single-block write using CPU

∙MMC/SD single-block write using EDMA

∙MMC/SD multiple-block read using CPU

∙MMC/SD multiple-block read using EDMA

∙MMC/SD multiple-block write using CPU

∙MMC/SD multiple-block write using EDMA

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MMC/SD card interface

1.5Industry Standard(s) Compliance Statement

The MMC/SD card controller supports the following industry standards (with the exception noted below):

∙MMC (Multimedia Card) Specification V3.31

∙SD (Secure Digital) Physical Layer Specification V1.1

The information in this document assumes that you are familiar with these standards.

The MMC/SD controller does not support the SPI mode of operation.

2Peripheral Architecture

The MMC/SD controller uses the MMC/SD protocol to communicate with the MMC/SD cards. You can configure the MMC/SD controller to work as an MMC or SD controller, based on the type of card the controller is communicating with. Figure 2 summarizes the MMC/SD mode interface. Figure 3 illustrates how the controller interfaces to the cards in MMC/SD mode.

In the MMC/SD mode, the MMC controller supports one or more MMC/SD cards. Regardless of the number of cards connected, the MMC/SD controller selects one by using identification broadcast on the data line. The following MMC/SD controller pins are used:

∙CMD: This pin is used for two-way communication between the connected card and the MMC/SD controller. The MMC/SD controller transmits commands to the card and the memory card drives responses to the commands on this pin.

∙DAT0 or DAT0-3: MMC cards only use one data line (DAT0) and SD cards use one or four data lines. The number of DAT pins (the data bus width) is set by the WIDTH bit in the MMC control register (MMCCTL), see Section 4.1).

∙CLK: This pin provides the clock to the memory card from the MMC/SD controller.

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Multimedia Card (MMC)/Secure Digital (SD) Card Controller

SPRUE30B –September 2006

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Supported Use Case Statement Industry Standards Compliance StatementMMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control1 MMC/SD Mode Write Sequence Signal DescriptionsMMC/SD Controller Pins Used in Each Mode Protocol Descriptions2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description CRC MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo RD CMDFifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten =1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Reset Considerations InitializationInitialize the Time-Out Registers Mmctor and Mmctod Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Data Block Registers Mmcblen and MmcnblkMonitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in MmcdrrChecking For a Data Transmit Empty Condition Interrupt Multiplexing Interrupt SupportInterrupt Events and Requests Description of MMC/SD Interrupt RequestsDMA Event Support Power ManagementEmulation Considerations MMC Card Identification Procedure Card Identification OperationProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPUMMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read OperationMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPUMMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read OperationOffset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description Clken Clkrt MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions ClkenMMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions FifofulEtrndne Edated Edrrdy Edxrdy MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions EtrndneMMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field DescriptionsMMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc NblkMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Transmit Register Mmcdxr Field DescriptionsDmatrig MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenBit Position Command Register Description Stream enableCRC7 Argh MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArglMMC Response Registers MMCRSP0-MMCRSP7 Bit Position of Response Register R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits MMCRSP4-0MMC Data Response Register Mmcdrsp MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Field DescriptionsAccwd Fifolev Fifodir Fiforst MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions AccwdTable A-1. Document Revision History Reference Additions/Modifications/DeletionsAppendix a Important Notice
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