Texas Instruments TMS320DM644x manual MMC/SD Mode Single-Block Write Operation Using CPU

Page 32

www.ti.com

Procedures for Common Operations

3.2MMC/SD Mode Single-Block Write Operation Using CPU

To perform a single-block write, the block length must be 512 bytes and the same length needs to be set in both the MMC/SD controller and the memory card. The procedure for this operation is:

1.Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the higher part of the address to MMCARGH and the low part of the address to MMCARGL.

2.Use the MMC command register (MMCCMD) to send the SELECT/DESELECT_CARD broadcast command. This selects the addressed card and deselects the others.

3.Write the destination start address to the MMC argument registers. Load the high part to the MMCARGH register and the low part to MMCARGL.

4.Read the card CSD to determine the card’s maximum block length.

5.Use MMCCMD to send the SET_BLOCKLEN command (if the block length is different than the length used in the previous operation). The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD.

6.Reset the FIFO (FIFORST bit in MMCFIFOCTL).

7.Set the FIFO direction to transmit (FIFODIR bit in MMCFIFOCTL).

8.Set the access width (ACCWD bits in MMCFIFOCTL).

9.Enable the MMC interrupt.

10.Enable the DXRDYINT interrupt.

11.Write the first 32 bytes of the data block to the data transmit register (MMCDXR).

12.Use MMCCMD to send the WRITE_BLOCK command to the card.

13.Wait for the MMC interrupt.

14.Use the MMC status register 0 (MMCST0) to check for errors and the status of the FIFO. If all of the data has not been written and if the FIFO is not full, go to step 15. If all of the data has been written, stop.

15.Write the next n bytes (this depends on the setting of the FIFOLEV bit in MMCFIFOCTL: 0 = 16 bytes, 1 = 32 bytes) of the data block to the MMC data transmit register (MMCDXR) and go to step 13.

The sequence of events in this operation is shown in Figure 14.

32

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

SPRUE30B –September 2006

Submit Documentation Feedback

Image 32

Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case Statement Industry Standards Compliance StatementMMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock ControlSignal Descriptions MMC/SD Controller Pins Used in Each Mode1 MMC/SD Mode Write Sequence Protocol DescriptionsPortion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence MMC/SD Mode Read Sequence Data Flow in the Input/Output FifoCRC RD CMDFifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten =1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Reset Considerations InitializationInitializing the Clock Controller Registers Mmcclk Initialize the Interrupt Mask Register MmcimInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and MmcnblkMonitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in MmcdrrChecking For a Data Transmit Empty Condition Interrupt Support Interrupt Events and RequestsInterrupt Multiplexing Description of MMC/SD Interrupt RequestsEmulation Considerations Power ManagementDMA Event Support MMC Card Identification Procedure Card Identification OperationProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPUMMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read OperationMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPUMMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read OperationOffset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions MMC Memory Clock Control Register Mmcclk MMC Memory Clock Control Register Mmcclk Field DescriptionsClken Clkrt ClkenBit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error MMC Status Register 1 MMCST1 MMC Status Register 1 MMCST1 Field DescriptionsFifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy FifofulMMC Interrupt Mask Register Mmcim MMC Interrupt Mask Register Mmcim Field DescriptionsEtrndne Edated Edrrdy Edxrdy EtrndneTOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field DescriptionsBlen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions MMC Number of Blocks Register Mmcnblk MMC Number of Blocks Counter Register MmcnblcMMC Number of Blocks Register Mmcnblk Field Descriptions NblkMMC Data Receive Register Mmcdrr MMC Data Transmit Register MmcdxrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field DescriptionsMMC Command Register Mmccmd MMC Command Register Mmccmd Field DescriptionsDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenCRC7 Stream enableBit Position Command Register Description MMC Argument Register Mmcarghl MMC Argument Register Mmcarghl Field DescriptionsArgh ArglMMC Response Registers MMCRSP0-MMCRSP7 R1, R3, R4, R5, or R6 Response 48 Bits R2 Response 136 BitsBit Position of Response Register MMCRSP4-0MMC Command Index Register Mmccidx MMC Command Index Register Mmccidx Field DescriptionsMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field DescriptionsMMC Fifo Control Register Mmcfifoctl MMC Fifo Control Register Mmcfifoctl Field DescriptionsAccwd Fifolev Fifodir Fiforst AccwdTable A-1. Document Revision History Reference Additions/Modifications/DeletionsAppendix a Important Notice