Texas Instruments TMS320DM644x manual MMC/SD Mode Multiple-Block Read Operation Using Edma

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Procedures for Common Operations

Figure 17. MMC/SD Mode Multiple-Block Read Operation

MMC controller register content

RCA ADDRESS HIGH

RCA ADDRESS LOW

SEL/DESEL. CARD

BLK ADDRESS HIGH

BLK ADDRESS LOW

SET_BLOCKLEN

READ_MULT_BLOCK

Is TOUTRD = 1?

Is CRCRD = 1?

Is DRRDY = 1?

NEXT DATA BYTE

STOP_TRANSMISSION

MMC controller

register

ARG HIGH

ARG LOW

COMMAND

ARG HIGH

ARG LOW

COMMAND

COMMAND

STATUS 0

DATA TX

COMMAND

Select one card with relative card address (RCA) while de−selecting the other cards.

Load starting block address into the high and low argument registers. Load block

length register with the block length value. Start the operation by loading a READ_MULTIPLE_BLOCK command into the command register.

Check TOUTRD bit to verify that the read operation has not timed−out. Check CRCRD bit for

any read CRC errors. Check DRRDY to see if a new byte is in the data receive register.

Terminate the multiple−block read operation.

3.9MMC/SD Mode Multiple-Block Read Operation Using EDMA

To perform a multiple-block read, the same block length must be set in both the MMC/SD controller and the card.

The procedure for this operation is as follows:

1.Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MMCARGH and the low part of the address to MMCARGL.

2.Read card CSD to determine the card'smaximum block length.

3.Use the MMC command register (MMCCMD) to send the SET_BLOCKLEN command (if the block length is different than the length used in the previous operation). The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD.

4.Reset the FIFO (FIFORST bit in MMCFIFOCTL).

5.Set the FIFO direction to receive (FIFODIR bit in MMCFIFOCTL).

6.Set the FIFO threshold (FIFOLEV bit in MMCFIFOCTL).

7.Set the access width (ACCWD bits in MMCFIFOCTL).

8.Set up DMA (DMA size needs to be greater than or equal to FIFOLEV setting).

9.Use MMCCMD to send the READ_MULTI_BLOCK command to the card.

10.Wait for DMA sequence to complete.

11.Use the MMC status register 0 (MMCST0) to check for errors.

12.Use MMCCMD to send the STOP_TRANSMISSION command.

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramProtocol Descriptions Signal DescriptionsMMC/SD Controller Pins Used in Each Mode 1 MMC/SD Mode Write SequenceMMC/SD Mode Write Sequence 2 MMC/SD Mode Read SequencePortion Sequence Description RD CMD MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo CRCFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 Fifo Operation During Card Read Operation Edma ReadsCPU Reads Fifo Operation During Card Read Diagram Fifo Operation During Card Write Operation Edma WritesCPU Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Data Block Registers Mmcblen and Mmcnblk Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Time-Out Registers Mmctor and MmctodDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Description of MMC/SD Interrupt Requests Interrupt SupportInterrupt Events and Requests Interrupt MultiplexingPower Management DMA Event SupportEmulation Considerations Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description MMC Control Register Mmcctl MMC Control Register Mmcctl Field DescriptionsBit Field Value Description Clken MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken ClkrtMMC Status Register 0 MMCST0 MMC Status Register 0 MMCST0 Field DescriptionsBit Field Write-data CRC error Fifoful MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp BusyEtrndne MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne Edated Edrrdy EdxrdyMMC Response Time-Out Register Mmctor MMC Response Time-Out Register Mmctor Field DescriptionsTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodMMC Block Length Register Mmcblen MMC Block Length Register Mmcblen Field DescriptionsBlen Nblk MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register Mmcnblk Field DescriptionsMMC Data Transmit Register Mmcdxr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Receive Register Mmcdrr Field DescriptionsDclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions DmatrigStream enable Bit Position Command Register DescriptionCRC7 Argl MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArghMMC Response Registers MMCRSP0-MMCRSP7 MMCRSP4-0 R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits Bit Position of Response RegisterMMC Data Response Register Mmcdrsp Field Descriptions MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register MmcdrspAccwd MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Fifolev Fifodir FiforstReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice
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