Texas Instruments TMS320DM644x manual MMC/SD Mode Multiple-Block Write Operation Using Edma

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Procedures for Common Operations

3.7MMC/SD Mode Multiple-Block Write Operation Using EDMA

To perform a multiple-block write, the same block length needs to be set in both the MMC/SD controller and the card. The procedure for this operation is:

1.Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MMCARGH and the low part of the address to MMCARGL.

2.Read card CSD to determine the card'smaximum block length.

3.Use the MMC command register (MMCCMD) to send the SET_BLOCKLEN command (if the block length is different than the length used in the previous operation). The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD.

4.Reset the FIFO (FIFORST bit in MMCFIFOCTL).

5.Set the FIFO direction to transmit (FIFODIR bit in MMCFIFOCTL).

6.Set the FIFO threshold (FIFOLEV bit in MMCFIFOCTL).

7.Set the access width (ACCWD bits in MMCFIFOCTL).

8.Set up DMA (DMA size needs to be greater than or equal to FIFOLEV setting).

9.Use MMCCMD to send the WRITE_MULTI_BLOCK command to the card (set DMATRIG bit in MMCCMD to trigger first DMA).

10.Wait for DMA sequence to complete or the DATADNE flag in the MMC status register 0 (MMCST0) is set.

11.Use MMCST0 to check for errors.

12.Use MMCCMD to send the STOP_TRANSMISSION command.

3.8MMC/SD Mode Multiple-Block Read Operation Using CPU

To perform a multiple-block read, the same block length needs to be set in both the MMC/SD controller and the card.

Note: The procedure in this section uses a STOP_TRANSMISSION command to end the block transfer. This assumes that the value in the MMC number of blocks counter register (MMCNBLK) is 0. A multiple-block operation terminates itself if you load MMCNBLK with the exact number of blocks you want transferred.

The procedure for this operation is:

1.Write the card’s relative address to the MMC argument registers (MMCARGH and MMCARGL). Load the high part of the address to MMCARGH and the low part of the address to MMCARGL.

2.Read card CSD to determine the card'smaximum block length.

3.Use the MMC command register (MMCCMD) to send the SET_BLOCKLEN command (if the block length is different than the length used in the previous operation). The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD.

4.Reset the FIFO (FIFORST bit in MMCFIFOCTL).

5.Set the FIFO direction to receive (FIFODIR bit in MMCFIFOCTL).

6.Set FIFO threshold (FIFOLEV bit in MMCFIFOCTL).

7.Set the access width (ACCWD bits in MMCFIFOCTL).

8.Enable the MMC interrupt.

9.Enable DRRDYINT interrupt.

10.Use MMCCMD to send the READ_MULT_BLOCKS command.

11.Wait for MMC interrupt.

12.Use the MMC status register 0 (MMCST0) to check for errors and to determine the status of the FIFO. If FIFO is not empty and more bytes are to be read, go to step 13. If the all of the data has been read, go to step 14.

13.Read n bytes (depends on setting of FIFOLEV in MMCFIFOCTL: 0 = 16 bytes, 1 = 32 bytes) of data from the MMC data receive register (MMCDRR) and go to step 10.

14.Use MMCCMD to send the STOP_TRANSMISSION command.

The sequence of events in this operation is shown in Figure 17.

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Multimedia Card (MMC)/Secure Digital (SD) Card Controller

SPRUE30B –September 2006

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Supported Use Case Statement Industry Standards Compliance StatementMMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control1 MMC/SD Mode Write Sequence Signal DescriptionsMMC/SD Controller Pins Used in Each Mode Protocol DescriptionsPortion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence CRC MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo RD CMDFifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten =1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Reset Considerations InitializationInitialize the Time-Out Registers Mmctor and Mmctod Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Data Block Registers Mmcblen and MmcnblkMonitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in MmcdrrChecking For a Data Transmit Empty Condition Interrupt Multiplexing Interrupt SupportInterrupt Events and Requests Description of MMC/SD Interrupt RequestsEmulation Considerations Power ManagementDMA Event Support MMC Card Identification Procedure Card Identification OperationProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPUMMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read OperationMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPUMMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read OperationOffset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions Clken Clkrt MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions ClkenBit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions FifofulEtrndne Edated Edrrdy Edxrdy MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions EtrndneTOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field DescriptionsBlen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc NblkMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Transmit Register Mmcdxr Field DescriptionsDmatrig MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenCRC7 Stream enableBit Position Command Register Description Argh MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArglMMC Response Registers MMCRSP0-MMCRSP7 Bit Position of Response Register R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits MMCRSP4-0MMC Data Response Register Mmcdrsp MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Field DescriptionsAccwd Fifolev Fifodir Fiforst MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions AccwdTable A-1. Document Revision History Reference Additions/Modifications/DeletionsAppendix a Important Notice
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