Texas Instruments TMS320DM644x Card Identification Operation, MMC Card Identification Procedure

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Procedures for Common Operations

3 Procedures for Common Operations

3.1Card Identification Operation

Before the MMC/SD controller starts data transfers to or from memory cards in the MMC/SD native mode, it must first identify how many cards are present on the bus and configure them. For each card that responds to the ALL_SEND_CID broadcast command, the controller reads that card’s unique card identification address (CID) and then assigns it a relative address (RCA). This address is much shorter than the CID and the MMC/SD controller uses this address to identify the card in all future commands that involve the card.

Only one card completes the response to ALL_SEND_CID at any one time. The absence of any response to ALL_SEND_CID indicates that all cards have been identified and configured.

Note: The following steps assume that the MMC/SD controller is configured to operate in MMC or SD mode, and the memory clock frequency on the CLK pin is set for 400 kHz or less.

The procedure for a card identification operation is issued in open-drain bus mode for both MMC and SD cards.

3.1.1MMC Card Identification Procedure

The MMC card identification procedure is:

1.Use the MMC command register (MMCCMD) to issue the GO_IDLE_STATE (CMD0) command to the MMC cards. Using MMCCMD to issue the CMD0 command puts all cards (MMC and SD) in the idle state and no response from the cards is expected.

2.Use MMCCMD to issue the SEND_OP_CMD (CMD1) command with the voltage range supported (R3 response, if it is successful; R1b response, if the card is expected to be busy). Using MMCCMD to issue the CMD1 command allows the host to identify and reject cards that do not match the VDD range that the host supports.

3.If the response in step 2 is R1b (that is, the card is still busy due to power up), then go back to step 2. If the card is not busy, continue to step 4.

4.Use MMCCMD to send the ALL_SEND_CID (CMD2) command (R2 response is expected) to the MMC cards. Using MMCCMD to send the CMD2 command notifies all cards to send their unique card identification (CID) number. There should only be one card that successfully sends its full CID number to the host. The successful card goes into the identification state and does not respond to this command again.

5.Use MMCMD to issue the SET_RELATIVE_ADDR (CMD3) command (R1 response is expected) in order to assign an address that is shorter than the CID number that will be used in the future to address the card in the future data transfer mode.

Note: This command is only addressed to the card that successfully sent its CID number in step 4. This card now goes into standby mode. This card also changes its output drivers from open-drain to push-pull. It stops replying to the CMD2 command, allowing for the identification of other cards.

6.Repeat step 4 and step 5 to identify and assign relative addresses to all remaining cards until no card responds to the CMD1 command. No card responding within 5 memory clock cycles indicates that all cards have been identified and the MMC card identification procedure terminates.

The sequence of events in this operation is shown in Figure 12.

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramMMC/SD Controller Pins Used in Each Mode Signal Descriptions1 MMC/SD Mode Write Sequence Protocol DescriptionsPortion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence Data Flow in the Input/Output Fifo MMC/SD Mode Read SequenceCRC RD CMDFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Interrupt Mask Register Mmcim Initializing the Clock Controller Registers MmcclkInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and MmcnblkDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Interrupt Events and Requests Interrupt SupportInterrupt Multiplexing Description of MMC/SD Interrupt RequestsEmulation Considerations Power ManagementDMA Event Support Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions MMC Memory Clock Control Register Mmcclk Field Descriptions MMC Memory Clock Control Register MmcclkClken Clkrt ClkenBit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error MMC Status Register 1 MMCST1 Field Descriptions MMC Status Register 1 MMCST1Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy FifofulMMC Interrupt Mask Register Mmcim Field Descriptions MMC Interrupt Mask Register MmcimEtrndne Edated Edrrdy Edxrdy EtrndneTOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodBlen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions MMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register MmcnblkMMC Number of Blocks Register Mmcnblk Field Descriptions NblkMMC Data Transmit Register Mmcdxr MMC Data Receive Register MmcdrrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field DescriptionsMMC Command Register Mmccmd Field Descriptions MMC Command Register MmccmdDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenCRC7 Stream enableBit Position Command Register Description MMC Argument Register Mmcarghl Field Descriptions MMC Argument Register MmcarghlArgh ArglMMC Response Registers MMCRSP0-MMCRSP7 R2 Response 136 Bits R1, R3, R4, R5, or R6 Response 48 BitsBit Position of Response Register MMCRSP4-0MMC Command Index Register Mmccidx Field Descriptions MMC Command Index Register MmccidxMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field DescriptionsMMC Fifo Control Register Mmcfifoctl Field Descriptions MMC Fifo Control Register MmcfifoctlAccwd Fifolev Fifodir Fiforst AccwdReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice
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