Texas Instruments TMS320DM644x manual MMC Control Register Mmcctl, Bit Field Value Description

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Registers

4.1MMC Control Register (MMCCTL)

The MMC control register (MMCCTL) is used to enable or configure various modes of the MMC controller. Set or clear the DATRST and CMDRST bits at the same time to reset or enable the MMC controller.

The MMC control register (MMCCTL) is shown in Figure 18 and described in Table 6.

Figure 18. MMC Control Register (MMCCTL)

31						16
		Reserved
		R-0
15			11	10	9	8
		Reserved		PERMDX	PERMDR	Reserved
		R-0		R/W-0	R/W-0	R-0
7	6	5	3	2	1	0
	DATEG	Reserved		WIDTH	CMDRST	DATRST
	R/W-0	R-0		R/W-0	R/W-0	R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

			Table 6. MMC Control Register (MMCCTL) Field Descriptions
Bit	Field	Value	Description
31-11	Reserved	0	Reserved
10	PERMDX		Endian select when writing.
		0	Little endian is selected.
		1	Big endian is selected.
9	PERMDR		Endian select when reading.
		0	Little endian is selected.
		1	Big endian is selected.
8	Reserved	0	Reserved
7-6	DATEG	0-3h	DAT3 edge detection select.
		0	DAT3 edge detection is disabled.
		1h	DAT3 rising-edge detection is enabled.
		2h	DAT3 falling-edge detection is enabled.
		3h	DAT3 rising-edge and falling-edge detections are enabled.
5-3	Reserved	0	Reserved
2	WIDTH		Data bus width (MMC mode only).
		0	Data bus has 1 bit (only DAT0 is used).
		1	Data bus has 4 bits (all DAT0-3 are used).
1	CMDRST		CMD logic reset.
		0	CMD line portion is enabled.
		1	CMD line portion is disabled and in reset state.
0	DATRST		DAT logic reset.
		0	DAT line portion is enabled.
		1	DAT line portion is disabled and in reset state.

SPRUE30B –September 2006	Multimedia Card (MMC)/Secure Digital (SD) Card Controller	41
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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramMMC/SD Controller Pins Used in Each Mode Signal Descriptions1 MMC/SD Mode Write Sequence Protocol DescriptionsPortion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence Data Flow in the Input/Output Fifo MMC/SD Mode Read SequenceCRC RD CMDFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Interrupt Mask Register Mmcim Initializing the Clock Controller Registers MmcclkInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and MmcnblkDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Interrupt Events and Requests Interrupt SupportInterrupt Multiplexing Description of MMC/SD Interrupt RequestsEmulation Considerations Power ManagementDMA Event Support Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions MMC Memory Clock Control Register Mmcclk Field Descriptions MMC Memory Clock Control Register MmcclkClken Clkrt ClkenBit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error MMC Status Register 1 MMCST1 Field Descriptions MMC Status Register 1 MMCST1Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy FifofulMMC Interrupt Mask Register Mmcim Field Descriptions MMC Interrupt Mask Register MmcimEtrndne Edated Edrrdy Edxrdy EtrndneTOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodBlen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions MMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register MmcnblkMMC Number of Blocks Register Mmcnblk Field Descriptions NblkMMC Data Transmit Register Mmcdxr MMC Data Receive Register MmcdrrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field DescriptionsMMC Command Register Mmccmd Field Descriptions MMC Command Register MmccmdDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenCRC7 Stream enableBit Position Command Register Description MMC Argument Register Mmcarghl Field Descriptions MMC Argument Register MmcarghlArgh ArglMMC Response Registers MMCRSP0-MMCRSP7 R2 Response 136 Bits R1, R3, R4, R5, or R6 Response 48 BitsBit Position of Response Register MMCRSP4-0MMC Command Index Register Mmccidx Field Descriptions MMC Command Index Register MmccidxMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field DescriptionsMMC Fifo Control Register Mmcfifoctl Field Descriptions MMC Fifo Control Register MmcfifoctlAccwd Fifolev Fifodir Fiforst AccwdReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice