Texas Instruments TMS320DM644x manual Monitoring Activity in the MMC/SD Mode

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Peripheral Architecture

2.9.7Monitoring Activity in the MMC/SD Mode

This section describes registers and specific register bits that you can use to obtain the status of the MMC/SD controller in the MMC/SD mode. You can determine the status of the MMC/SD controller by reading the bits in the MMC status register 0 (MMCST0) and MMC status register 1 (MMCST1).

2.9.7.1Determining Whether New Data is Available in MMCDRR

The MMC/SD controller sets the DRRDY bit in MMCST0 when the data in the FIFO is greater than the threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled (EDRRDY = 1 in MMCIM), the ARM is notified of the event by an interrupt. A read of the MMC data receive register (MMCDDR) clears the DRRDY flag.

2.9.7.2Verifying that MMCDXR is Ready to Accept New Data

The MMC/SD controller sets the DXRDY bit in MMCST0 when the amount of data in the FIFO is less than the threshold set in the MMC FIFO control register (MMCFIFOCTL). If the interrupt request is enabled (EDXRDY = 1 in MMCIM), the ARM is notified of the event by an interrupt.

2.9.7.3Checking for CRC Errors

The MMC/SD controller sets the CRCRS, CRCRD, and CRCWR bits in MMCST0 in response to the corresponding CRC errors of command response, data read, and data write. If the interrupt request is enabled (ECRCRS/ECRCRD/ECRCWR = 1 in MMCIM), the ARM is notified of the CRC error by an interrupt.

2.9.7.4Checking for Time-Out Events

The MMC/SD controller sets the TOUTRS and TOUTRD bits in MMCST0 in response to the corresponding command response or data read time-out event. If the interrupt request is enabled (ETOUTRS/ETOUTRD = 1 in MMCIM), the ARM is notified of the event by an interrupt.

2.9.7.5Determining When a Response/Command is Done

The MMC/SD controller sets the RSPDNE bit in MMCST0 when the response is done; or in the case of commands that do not require a response, when the command is done. If the interrupt request is enabled (ERSPDNE = 1 in MMCIM), the ARM is also notified.

2.9.7.6Determining Whether the Memory Card is Busy

The card sends a busy signal either when waiting for an R1b-type response or when programming the last write data into its flash memory. The MMC/SD controller has two flags to notify you whether the memory card is sending a busy signal. The two flags are complements of each other:

∙The BSYDNE flag in MMCST0 is set if the card did not send or is not sending a busy signal when the MMC/SD controller is expecting a busy signal (BSYEXP = 1 in MMCCMD). The interrupt by this bit is enabled by a corresponding interrupt enable bit (EBSYDNE = 1 in MMCIM).

∙The BUSY flag in MMCST1 is set when a busy signal is received from the card.

2.9.7.7Determining Whether a Data Transfer is Done

The MMC/SD controller sets the DATDNE bit in MMCST0 when all of the bytes of a data transfer have been transmitted/received. The DATDNE bit is polled to determine when to stop writing to the data transmit register (for a write operation) or when to stop reading from the data receive register (for a read operation). The ARM is also notified of the time-out event by an interrupt if the interrupt request is enabled (EDATDNE = 1 in MMCIM).

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramMMC/SD Controller Pins Used in Each Mode Signal Descriptions1 MMC/SD Mode Write Sequence Protocol Descriptions2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description Data Flow in the Input/Output Fifo MMC/SD Mode Read SequenceCRC RD CMDFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Interrupt Mask Register Mmcim Initializing the Clock Controller Registers MmcclkInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and MmcnblkDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Interrupt Events and Requests Interrupt SupportInterrupt Multiplexing Description of MMC/SD Interrupt RequestsDMA Event Support Power ManagementEmulation Considerations Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description MMC Memory Clock Control Register Mmcclk Field Descriptions MMC Memory Clock Control Register MmcclkClken Clkrt ClkenMMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error MMC Status Register 1 MMCST1 Field Descriptions MMC Status Register 1 MMCST1Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy FifofulMMC Interrupt Mask Register Mmcim Field Descriptions MMC Interrupt Mask Register MmcimEtrndne Edated Edrrdy Edxrdy EtrndneMMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodMMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen MMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register MmcnblkMMC Number of Blocks Register Mmcnblk Field Descriptions NblkMMC Data Transmit Register Mmcdxr MMC Data Receive Register MmcdrrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field DescriptionsMMC Command Register Mmccmd Field Descriptions MMC Command Register MmccmdDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenBit Position Command Register Description Stream enableCRC7 MMC Argument Register Mmcarghl Field Descriptions MMC Argument Register MmcarghlArgh ArglMMC Response Registers MMCRSP0-MMCRSP7 R2 Response 136 Bits R1, R3, R4, R5, or R6 Response 48 BitsBit Position of Response Register MMCRSP4-0MMC Command Index Register Mmccidx Field Descriptions MMC Command Index Register MmccidxMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field DescriptionsMMC Fifo Control Register Mmcfifoctl Field Descriptions MMC Fifo Control Register MmcfifoctlAccwd Fifolev Fifodir Fiforst AccwdReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice
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