Texas Instruments TMS320DM644x manual Signal Descriptions, Protocol Descriptions

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Peripheral Architecture

2.2Signal Descriptions

Table 1 shows the MMC/SD controller pins that each mode uses. The MMC/SD protocol uses the clock, command (two-way communication between the MMC controller and memory card), and data (DAT0 for MMC card, DAT0-3 for SD card) pins.

Table 1. MMC/SD Controller Pins Used in Each Mode

 

 

 

Function

 

Type(1)

MMC and SD (1-bit mode)

SD (4-bit mode)

Pin

Communications

Communications

CLK

O

Clock line

Clock line

CMD

I/O

Command line

Command line

DAT0

I/O

Data line 0

Data line 0

DAT1

I/O

(Not used)

Data line 1

DAT2

I/O

(Not used)

Data line 2

DAT3

I/O

(Not used)

Data line 3

(1)I = input to the MMC controller; O = output from the MMC controller.

2.3Protocol Descriptions

The MMC/SD controller follows the MMC/SD protocol for completing any kind of transaction with the multimedia card and secure digital cards. For more detailed information, refer to the supported MMC and SD specifications in Section 1.5.

2.3.1MMC/SD Mode Write Sequence

Figure 5 and Table 2 show the signal activity when the MMC/SD controller is in the MMC/SD mode and is writing data to a memory card. The same block length must be defined in the MMC/SD controller and in the memory card before initiating a data write. In a successful write protocol sequence, the following steps occur:

∙The MMC/SD controller requests the CSD content.

∙The card receives the command and sends the content of the CSD register as its response.

∙If the desired block length, WRITE_BL_LEN value, is different from the default value determined from the response, the MMC/SD controller sends the block length command.

∙The card receives the command and sends responses to the command.

∙The MMC/SD controller requests the card to change states from standby to transfer.

∙The card receives the command and sends responses to the command.

∙The MMC/SD controller sends a write command to the card.

∙The card receives the command and sends responses to the command.

∙The MMC/SD controller sends a block of data to the card.

∙The card sends the CRC status to the MMC/SD controller.

∙The card sends a low BUSY bit until all of the data has been programmed into the flash memory inside the card.

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramMMC/SD Controller Pins Used in Each Mode Signal Descriptions1 MMC/SD Mode Write Sequence Protocol Descriptions2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description Data Flow in the Input/Output Fifo MMC/SD Mode Read SequenceCRC RD CMDFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Interrupt Mask Register Mmcim Initializing the Clock Controller Registers MmcclkInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and MmcnblkDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Interrupt Events and Requests Interrupt SupportInterrupt Multiplexing Description of MMC/SD Interrupt RequestsDMA Event Support Power ManagementEmulation Considerations Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description MMC Memory Clock Control Register Mmcclk Field Descriptions MMC Memory Clock Control Register MmcclkClken Clkrt ClkenMMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error MMC Status Register 1 MMCST1 Field Descriptions MMC Status Register 1 MMCST1Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy FifofulMMC Interrupt Mask Register Mmcim Field Descriptions MMC Interrupt Mask Register MmcimEtrndne Edated Edrrdy Edxrdy EtrndneMMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodMMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen MMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register MmcnblkMMC Number of Blocks Register Mmcnblk Field Descriptions NblkMMC Data Transmit Register Mmcdxr MMC Data Receive Register MmcdrrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field DescriptionsMMC Command Register Mmccmd Field Descriptions MMC Command Register MmccmdDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenBit Position Command Register Description Stream enableCRC7 MMC Argument Register Mmcarghl Field Descriptions MMC Argument Register MmcarghlArgh ArglMMC Response Registers MMCRSP0-MMCRSP7 R2 Response 136 Bits R1, R3, R4, R5, or R6 Response 48 BitsBit Position of Response Register MMCRSP4-0MMC Command Index Register Mmccidx Field Descriptions MMC Command Index Register MmccidxMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field DescriptionsMMC Fifo Control Register Mmcfifoctl Field Descriptions MMC Fifo Control Register MmcfifoctlAccwd Fifolev Fifodir Fiforst AccwdReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice
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