Texas Instruments TMS320DM644x MMC Interrupt Mask Register Mmcim, Etrndne Edated Edrrdy Edxrdy

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Registers

4.5MMC Interrupt Mask Register (MMCIM)

The MMC interrupt mask register (MMCIM) is used to enable (bit = 1) or disable (bit = 0) status interrupts. If an interrupt is enabled, the transition from 0 to 1 of the corresponding interrupt bit in the MMC status register 0 (MMCST0) can cause an interrupt signal to be sent to the CPU.

The MMC interrupt mask register (MMCIM) is shown in Figure 22 and described in Table 10.

Figure 22. MMC Interrupt Mask Register (MMCIM)

31							16
			Reserved
				R-0
15		13	12	11	10	9	8
	Reserved		ETRNDNE	EDATED	EDRRDY	EDXRDY	Reserved
	R-0		R/W-0	R/W-0	R/W-0	R/W-0	R-0
7	6	5	4	3	2	1	0
ECRCRS	ECRCRD	ECRCWR	ETOUTRS	ETOUTRD	ERSPDNE	EBSYDNE	EDATDNE
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions

Bit	Field	Value	Description
31-13	Reserved	0	Reserved
12	ETRNDNE		Transfer done (TRNDNE) interrupt enable.
		0	Transfer done interrupt is disabled.
		1	Transfer done interrupt is enabled.
11	EDATED		DAT3 edge detect (DATED) interrupt enable.
		0	DAT3 edge detect interrupt is disabled.
		1	DAT3 edge detect interrupt is enabled.
10	EDRRDY		Data receive register ready (DRRDY) interrupt enable.
		0	Data receive register ready interrupt is disabled.
		1	Data receive register ready interrupt is enabled.
9	EDXRDY		Data transmit register (MMCDXR) ready interrupt enable.
		0	Data transmit register ready interrupt is disabled.
		1	Data transmit register ready interrupt is enabled.
8	Reserved	0	Reserved
7	ECRCRS		Response CRC error (CRCRS) interrupt enable.
		0	Response CRC error interrupt is disabled.
		1	Response CRC error interrupt is enabled.
6	ECRCRD		Read-data CRC error (CRCRD) interrupt enable.
		0	Read-data CRC error interrupt is disabled.
		1	Read-data CRC error interrupt is enabled.
5	ECRCWR		Write-data CRC error (CRCWR) interrupt enable.
		0	Write-data CRC error interrupt is disabled.
		1	Write-data CRC error interrupt is disabled.
4	ETOUTRS		Response time-out event (TOUTRS) interrupt enable.
		0	Response time-out event interrupt is disabled.
		1	Response time-out event interrupt is enabled.

46	Multimedia Card (MMC)/Secure Digital (SD) Card Controller	SPRUE30B –September 2006
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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Supported Use Case Statement Industry Standards Compliance StatementMMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control1 MMC/SD Mode Write Sequence Signal DescriptionsMMC/SD Controller Pins Used in Each Mode Protocol Descriptions2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description CRC MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo RD CMDFifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten =1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Reset Considerations InitializationInitialize the Time-Out Registers Mmctor and Mmctod Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Data Block Registers Mmcblen and MmcnblkMonitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in MmcdrrChecking For a Data Transmit Empty Condition Interrupt Multiplexing Interrupt SupportInterrupt Events and Requests Description of MMC/SD Interrupt RequestsDMA Event Support Power ManagementEmulation Considerations MMC Card Identification Procedure Card Identification OperationProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPUMMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read OperationMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPUMMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read OperationOffset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description Clken Clkrt MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions ClkenMMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions FifofulEtrndne Edated Edrrdy Edxrdy MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions EtrndneMMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field DescriptionsMMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc NblkMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Transmit Register Mmcdxr Field DescriptionsDmatrig MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenBit Position Command Register Description Stream enableCRC7 Argh MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArglMMC Response Registers MMCRSP0-MMCRSP7 Bit Position of Response Register R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits MMCRSP4-0MMC Data Response Register Mmcdrsp MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Field DescriptionsAccwd Fifolev Fifodir Fiforst MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions AccwdTable A-1. Document Revision History Reference Additions/Modifications/DeletionsAppendix a Important Notice