Texas Instruments TMS320DM644x manual MMC Data Read Time-Out Register Mmctod

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Registers

4.7MMC Data Read Time-Out Register (MMCTOD)

The MMC data read time-out register (MMCTOD) defines how long the MMC controller waits for the data from a memory card before recording a time-out condition in the TOUTRD bit of the MMC status register 0 (MMCST0). If the corresponding ETOUTRD bit in the MMC interrupt mask register (MMCIM) is set, an interrupt is generated when the TOUTRD bit is set in MMCST0. If a memory card should require a longer time-out period than MMCTOD can provide, a software time-out mechanism can be implemented.

The MMC data read time-out register (MMCTOD) is shown in Figure 24 and described in Table 12.

	Figure 24. MMC Data Read Time-Out Register (MMCTOD)
31	16
	Reserved
	R-0
15	0

TOD_15_0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 12. MMC Data Read Time-Out Register (MMCTOD) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15-0	TOD_15_0	0-1F FFFFh	Data read time-out count. Used in conjunction with the TOD_20_16 bits in MMCTOR to form a
			21-bit count. See MMCTOR (Section 4.6).
		0	No time out
		1-FFFFh	1 CLK clock cycle to 2 097 151 CLK clock cycles

48	Multimedia Card (MMC)/Secure Digital (SD) Card Controller	SPRUE30B –September 2006
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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Features Functional Block DiagramPurpose of the Peripheral Supported Use Case Statement Industry Standards Compliance StatementMMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock ControlSignal Descriptions MMC/SD Controller Pins Used in Each Mode1 MMC/SD Mode Write Sequence Protocol DescriptionsMMC/SD Mode Write Sequence 2 MMC/SD Mode Read SequencePortion Sequence Description MMC/SD Mode Read Sequence Data Flow in the Input/Output FifoCRC RD CMDFifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten =1st 2nd 3rd 4th Support byten = 1111 1110 Fifo Operation During Card Read Operation Edma ReadsCPU Reads Fifo Operation During Card Read Diagram Fifo Operation During Card Write Operation Edma WritesCPU Writes Fifo Operation During Card Write Diagram Reset Considerations InitializationInitializing the Clock Controller Registers Mmcclk Initialize the Interrupt Mask Register MmcimInitialize the Time-Out Registers Mmctor and Mmctod Initialize the Data Block Registers Mmcblen and MmcnblkMonitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in MmcdrrChecking For a Data Transmit Empty Condition Interrupt Support Interrupt Events and RequestsInterrupt Multiplexing Description of MMC/SD Interrupt RequestsPower Management DMA Event SupportEmulation Considerations MMC Card Identification Procedure Card Identification OperationProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPUMMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read OperationMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPUMMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read OperationOffset Acronym Register Description MMC Control Register Mmcctl MMC Control Register Mmcctl Field DescriptionsBit Field Value Description MMC Memory Clock Control Register Mmcclk MMC Memory Clock Control Register Mmcclk Field DescriptionsClken Clkrt ClkenMMC Status Register 0 MMCST0 MMC Status Register 0 MMCST0 Field DescriptionsBit Field Write-data CRC error MMC Status Register 1 MMCST1 MMC Status Register 1 MMCST1 Field DescriptionsFifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy FifofulMMC Interrupt Mask Register Mmcim MMC Interrupt Mask Register Mmcim Field DescriptionsEtrndne Edated Edrrdy Edxrdy EtrndneMMC Response Time-Out Register Mmctor MMC Response Time-Out Register Mmctor Field DescriptionsTOR MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field DescriptionsMMC Block Length Register Mmcblen MMC Block Length Register Mmcblen Field DescriptionsBlen MMC Number of Blocks Register Mmcnblk MMC Number of Blocks Counter Register MmcnblcMMC Number of Blocks Register Mmcnblk Field Descriptions NblkMMC Data Receive Register Mmcdrr MMC Data Transmit Register MmcdxrMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Transmit Register Mmcdxr Field DescriptionsMMC Command Register Mmccmd MMC Command Register Mmccmd Field DescriptionsDmatrig Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenStream enable Bit Position Command Register DescriptionCRC7 MMC Argument Register Mmcarghl MMC Argument Register Mmcarghl Field DescriptionsArgh ArglMMC Response Registers MMCRSP0-MMCRSP7 R1, R3, R4, R5, or R6 Response 48 Bits R2 Response 136 BitsBit Position of Response Register MMCRSP4-0MMC Command Index Register Mmccidx MMC Command Index Register Mmccidx Field DescriptionsMMC Data Response Register Mmcdrsp MMC Data Response Register Mmcdrsp Field DescriptionsMMC Fifo Control Register Mmcfifoctl MMC Fifo Control Register Mmcfifoctl Field DescriptionsAccwd Fifolev Fifodir Fiforst AccwdTable A-1. Document Revision History Reference Additions/Modifications/DeletionsAppendix a Important Notice