Texas Instruments TMS320DM644x manual MMC Response Registers MMCRSP0-MMCRSP7

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Registers

4.15 MMC Response Registers (MMCRSP0-MMCRSP7)

Each command has a preset response type. When the MMC controller receives a response, it is stored in some or all of the eight MMC response registers (MMCRSP7-MMCRSP0). The response registers are updated as the responses arrive, even if the CPU has not read the previous contents.

As shown in Figure 33, Figure 34, Figure 35, and Figure 36 each of the MMC response registers holds up to 16 bits. Table 21 and Table 22 show the format for each type of response and which MMC response registers are used for the bits of the response. The first byte of the response is a command index byte and is stored in the MMC command index register (MMCCIDX).

	Figure 33. MMC Response Register 0 and 1 (MMCRSP01)
31	16
	MMCRSP1
	R/W-0
15	0

MMCRSP0

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

	Figure 34. MMC Response Register 2 and 3 (MMCRSP23)
31	16
	MMCRSP3
	R/W-0
15	0

MMCRSP2

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

	Figure 35. MMC Response Register 4 and 5 (MMCRSP45)
31	16
	MMCRSP5
	R/W-0
15	0

MMCRSP4

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

	Figure 36. MMC Response Register 6 and 7 (MMCRSP67)
31	16
	MMCRSP7
	R/W-0
15	0
	MMCRSP6

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

SPRUE30B –September 2006	Multimedia Card (MMC)/Secure Digital (SD) Card Controller	55
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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramProtocol Descriptions Signal DescriptionsMMC/SD Controller Pins Used in Each Mode 1 MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description RD CMD MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo CRCFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Data Block Registers Mmcblen and Mmcnblk Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Time-Out Registers Mmctor and MmctodDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Description of MMC/SD Interrupt Requests Interrupt SupportInterrupt Events and Requests Interrupt MultiplexingDMA Event Support Power ManagementEmulation Considerations Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description Clken MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken ClkrtMMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error Fifoful MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp BusyEtrndne MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne Edated Edrrdy EdxrdyMMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodMMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen Nblk MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register Mmcnblk Field DescriptionsMMC Data Transmit Register Mmcdxr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Receive Register Mmcdrr Field DescriptionsDclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions DmatrigBit Position Command Register Description Stream enableCRC7 Argl MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArghMMC Response Registers MMCRSP0-MMCRSP7 MMCRSP4-0 R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits Bit Position of Response RegisterMMC Data Response Register Mmcdrsp Field Descriptions MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register MmcdrspAccwd MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Fifolev Fifodir FiforstReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice