Texas Instruments TMS320DM644x manual Table A-1. Document Revision History

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Appendix A

Appendix A Revision History

Table A-1lists the changes made since the previous version of this document.

Table A-1. Document Revision History

Reference Additions/Modifications/Deletions

Section 1.2 Changed third bullet.

Added seventh bullet.

Section 1.3 Added second sentence.

Section 1.5 Deleted third bullet.

Section 2 Changed second sentence in second paragraph.

Figure 3 Changed Figure 3.

Section 2.1 Changed first sentence in second paragraph.

Figure 4 Changed Figure 4.

Table 1 Changed table headings.

Section 2.3.1 Changed Section 2.3.1.

Section 2.3.2 Changed Section 2.3.2.

Section 2.4 Added fourth sentence.

Changed first bullet.

Figure 7 Changed Figure 7.

Section 2.5 Changed first sentence.

Changed last sentence.

Section 2.6.1 Changed third sentence in second paragraph.

Section 2.6.2 Added second paragraph.

Section 2.7.1 Changed first sentence.

Added last sentence.

Changed second sentence in second paragraph.

Section 2.7.2 Added second paragraph.

Added Note.

Section 2.9.1 Changed section title.

Added Note after fourth bullet.

Section 2.9.2 Changed first sentence.

Deleted second paragraph.

Section 2.9.7 Deleted subsection 2.9.7.1: Detecting Edges on the DAT3 Pin

Deleted subsection 2.9.7.2: Detecting Level Changes on the DAT3 Pin

Section 2.10.1 Changed second paragraph.

Added Note.

Section 3.1 Changed Section 3.1.

Added Section 3.1.1.

Added Section 3.1.2.

Section 3.9 Deleted section 3.10: SDIO Card Function

Table 5 Changed Table 5.

Section 4 Deleted section 4.18: SDIO Control Register (SDIOCTL)

Deleted section 4.19: SDIO Status Register 0 (SDIOST0)

Deleted section 4.20: SDIO Interrupt Enable Register (SDIOIEN)

Deleted section 4.21: SDIO Interrupt Status Register (SDIOIST)

SPRUE30B –September 2006	Revision History	59
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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramProtocol Descriptions Signal DescriptionsMMC/SD Controller Pins Used in Each Mode 1 MMC/SD Mode Write SequencePortion Sequence Description MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence RD CMD MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo CRCFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 CPU Reads Fifo Operation During Card Read OperationEdma Reads Fifo Operation During Card Read Diagram CPU Writes Fifo Operation During Card Write OperationEdma Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Data Block Registers Mmcblen and Mmcnblk Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Time-Out Registers Mmctor and MmctodDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Description of MMC/SD Interrupt Requests Interrupt SupportInterrupt Events and Requests Interrupt MultiplexingEmulation Considerations Power ManagementDMA Event Support Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description Bit Field Value Description MMC Control Register MmcctlMMC Control Register Mmcctl Field Descriptions Clken MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken ClkrtBit Field MMC Status Register 0 MMCST0MMC Status Register 0 MMCST0 Field Descriptions Write-data CRC error Fifoful MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp BusyEtrndne MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne Edated Edrrdy EdxrdyTOR MMC Response Time-Out Register MmctorMMC Response Time-Out Register Mmctor Field Descriptions MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodBlen MMC Block Length Register MmcblenMMC Block Length Register Mmcblen Field Descriptions Nblk MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register Mmcnblk Field DescriptionsMMC Data Transmit Register Mmcdxr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Receive Register Mmcdrr Field DescriptionsDclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions DmatrigCRC7 Stream enableBit Position Command Register Description Argl MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArghMMC Response Registers MMCRSP0-MMCRSP7 MMCRSP4-0 R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits Bit Position of Response RegisterMMC Data Response Register Mmcdrsp Field Descriptions MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register MmcdrspAccwd MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Fifolev Fifodir FiforstReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice