Texas Instruments TMS320DM644x Fifo Operation During Card Read Operation, Edma Reads, CPU Reads

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Peripheral Architecture

2.6FIFO Operation During Card Read Operation

2.6.1EDMA Reads

The FIFO controller manages the activities of reading the data in from the card and issuing EDMA read events. Each time an EDMA read event is issued, an EDMA read request interrupt generates.

Figure 10 provides details of the FIFO controllers operation. As data is received from the card, it is read into the FIFO. When the number of bytes of data received is equal to the level set by the FIFOLEV bits in MMCFIFOCTL, an EDMA read event is issued and new EDMA events are disabled until the EDMA is done with the transfer issued by the current event. Data is read from the FIFO by way of MMCDRR. The FIFO controller continues to read in data from the card while checking for the EDMA event to occur or for the FIFO to become full. Once the EDMA event finishes, new EDMA events are enabled. If the FIFO fills up, the FIFO controller stops the MMC/SD controller from reading any more data until the FIFO is no longer full.

An EDMA read event generates when the last data arrives, as determined by the MMC block length register (MMCBLEN) and the MMC number of blocks register (MMCNBLK) settings. This EDMA event flushes all of the data that was read from the card from the FIFO.

Each time an EDMA read event generates, an interrupt (DRRDYINT) generates and the DRRDY bit in the MMC status register 0 (MMCST0) is also set.

2.6.2CPU Reads

The system CPU can also directly read the card data by reading the MMC data receive register (MMCDRR). The MMC/SD peripheral supports reads that are 1, 2, 3, or 4 bytes wide as, shown in Figure 8 and Figure 9.

As data is received from the card, it is read into the FIFO. When the number of bytes of data received is equal to the level set by the FIFOLEV bits in MMCFIFOCTL, a DRRDYINT interrupt is issued and the DRRDY bit in the MMC status register 0 (MMCST0) is set. Upon receiving the interrupt, the CPU quickly reads out the bytes received (equal to the level set by the FIFOLEV bits). A DRRDYINT interrupt also generates when the last data arrives as determined by the MMC block length register (MMCBLEN) and the MMC numbers of blocks register (MMCNBLK) settings.

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramProtocol Descriptions Signal DescriptionsMMC/SD Controller Pins Used in Each Mode 1 MMC/SD Mode Write Sequence2 MMC/SD Mode Read Sequence MMC/SD Mode Write SequencePortion Sequence Description RD CMD MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo CRCFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 Edma Reads Fifo Operation During Card Read OperationCPU Reads Fifo Operation During Card Read Diagram Edma Writes Fifo Operation During Card Write OperationCPU Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Data Block Registers Mmcblen and Mmcnblk Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Time-Out Registers Mmctor and MmctodDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Description of MMC/SD Interrupt Requests Interrupt SupportInterrupt Events and Requests Interrupt MultiplexingDMA Event Support Power ManagementEmulation Considerations Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description MMC Control Register Mmcctl Field Descriptions MMC Control Register MmcctlBit Field Value Description Clken MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken ClkrtMMC Status Register 0 MMCST0 Field Descriptions MMC Status Register 0 MMCST0Bit Field Write-data CRC error Fifoful MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp BusyEtrndne MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne Edated Edrrdy EdxrdyMMC Response Time-Out Register Mmctor Field Descriptions MMC Response Time-Out Register MmctorTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodMMC Block Length Register Mmcblen Field Descriptions MMC Block Length Register MmcblenBlen Nblk MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register Mmcnblk Field DescriptionsMMC Data Transmit Register Mmcdxr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Receive Register Mmcdrr Field DescriptionsDclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions DmatrigBit Position Command Register Description Stream enableCRC7 Argl MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArghMMC Response Registers MMCRSP0-MMCRSP7 MMCRSP4-0 R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits Bit Position of Response RegisterMMC Data Response Register Mmcdrsp Field Descriptions MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register MmcdrspAccwd MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Fifolev Fifodir FiforstReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice
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