Texas Instruments TMS320DM644x Data Flow in the Input/Output Fifo, MMC/SD Mode Read Sequence, Crc

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Peripheral Architecture

Figure 6. MMC/SD Mode Read Sequence Timing Diagram

CMD
1 transfer	2 CRC
source bit	bytes
Data
Start	End
bit	bit

CLK

	Table 3. MMC/SD Mode Read Sequence
Portion of the
Sequence	Description
RD CMD	Read command: A 6-byte READ_SINGLE_BLOCK command token is sent from the ARM to the card.
CMD RSP	Command response: The card sends a response of type R1 to acknowledge the READ_SINGLE_BLOCK
	command to the ARM.
DAT BLK	Data block: The card sends a block of data to the ARM. The data content is preceded by a start bit and is
	followed by two CRC byte and an end bit.

2.4Data Flow in the Input/Output FIFO

The MMC/SD controller contains a single 256-bit FIFO that is used for both reading data from the memory card and writing data to the memory card (see Figure 7). The FIFO is organized as 32 eight-bit entries. The conversion from the 32-bit bus to the byte format of the FIFO follows the little-endian convention (details are provided in later sections). The read and write FIFOs act as an interim location to store data transferred from/to the card momentarily via the CPU or EDMA. The FIFO includes logic to generate EDMA events and interrupts based on the amount of data in the FIFO and a programmable number of bytes received/transmitted. Flags are set when the FIFO is full or empty.

SPRUE30B –September 2006

Multimedia Card (MMC)/Secure Digital (SD) Card Controller

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Supported Use Case StatementMMC/SD Controller Interface Diagram Clock Control MMC/SD Controller Clocking DiagramProtocol Descriptions Signal DescriptionsMMC/SD Controller Pins Used in Each Mode 1 MMC/SD Mode Write SequenceMMC/SD Mode Write Sequence 2 MMC/SD Mode Read SequencePortion Sequence Description RD CMD MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo CRCFifo Operation Diagram 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten = Data Flow in the Data Registers Mmcdrr and Mmcdxr1st 2nd 3rd 4th Support byten = 1111 1110 Fifo Operation During Card Read Operation Edma ReadsCPU Reads Fifo Operation During Card Read Diagram Fifo Operation During Card Write Operation Edma WritesCPU Writes Fifo Operation During Card Write Diagram Initialization Reset ConsiderationsInitialize the Data Block Registers Mmcblen and Mmcnblk Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Time-Out Registers Mmctor and MmctodDetermining Whether New Data is Available in Mmcdrr Monitoring Activity in the MMC/SD ModeChecking For a Data Transmit Empty Condition Description of MMC/SD Interrupt Requests Interrupt SupportInterrupt Events and Requests Interrupt MultiplexingPower Management DMA Event SupportEmulation Considerations Card Identification Operation MMC Card Identification ProcedureProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Read Operation Using the CPU MMC/SD Mode Single-Block Write Operation Using the EdmaMMC/SD Mode Single-Block Read Operation MMC/SD Mode Single-Block Read Operation Using EdmaMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Read Operation Using CPU MMC/SD Mode Multiple-Block Write Operation Using EdmaMMC/SD Mode Multiple-Block Read Operation MMC/SD Mode Multiple-Block Read Operation Using EdmaOffset Acronym Register Description MMC Control Register Mmcctl MMC Control Register Mmcctl Field DescriptionsBit Field Value Description Clken MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions Clken ClkrtMMC Status Register 0 MMCST0 MMC Status Register 0 MMCST0 Field DescriptionsBit Field Write-data CRC error Fifoful MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp BusyEtrndne MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions Etrndne Edated Edrrdy EdxrdyMMC Response Time-Out Register Mmctor MMC Response Time-Out Register Mmctor Field DescriptionsTOR MMC Data Read Time-Out Register Mmctod Field Descriptions MMC Data Read Time-Out Register MmctodMMC Block Length Register Mmcblen MMC Block Length Register Mmcblen Field DescriptionsBlen Nblk MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc MMC Number of Blocks Register Mmcnblk Field DescriptionsMMC Data Transmit Register Mmcdxr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Receive Register Mmcdrr Field DescriptionsDclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp Pplen MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions DmatrigStream enable Bit Position Command Register DescriptionCRC7 Argl MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArghMMC Response Registers MMCRSP0-MMCRSP7 MMCRSP4-0 R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits Bit Position of Response RegisterMMC Data Response Register Mmcdrsp Field Descriptions MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register MmcdrspAccwd MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions Accwd Fifolev Fifodir FiforstReference Additions/Modifications/Deletions Table A-1. Document Revision HistoryAppendix a Important Notice