Texas Instruments TMS320DM644x manual List of Tables

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	List of Tables
1	MMC/SD Controller Pins Used in Each Mode	13
2	MMC/SD Mode Write Sequence	14
3	MMC/SD Mode Read Sequence	15
4	Description of MMC/SD Interrupt Requests	27
5	Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers	40
6	MMC Control Register (MMCCTL) Field Descriptions	41
7	MMC Memory Clock Control Register (MMCCLK) Field Descriptions	42
8	MMC Status Register 0 (MMCST0) Field Descriptions	43
9	MMC Status Register 1 (MMCST1) Field Descriptions	45
10	MMC Interrupt Mask Register (MMCIM) Field Descriptions	46
11	MMC Response Time-Out Register (MMCTOR) Field Descriptions	47
12	MMC Data Read Time-Out Register (MMCTOD) Field Descriptions	48
13	MMC Block Length Register (MMCBLEN) Field Descriptions	49
14	MMC Number of Blocks Register (MMCNBLK) Field Descriptions	50
15	MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions	50
16	MMC Data Receive Register (MMCDRR) Field Descriptions	51
17	MMC Data Transmit Register (MMCDXR) Field Descriptions	51
18	MMC Command Register (MMCCMD) Field Descriptions	52
19	Command Format	53
20	MMC Argument Register (MMCARGHL) Field Descriptions	54
21	R1, R3, R4, R5, or R6 Response (48 Bits)	56
22	R2 Response (136 Bits)	56
23	MMC Data Response Register (MMCDRSP) Field Descriptions	57
24	MMC Command Index Register (MMCCIDX) Field Descriptions	57
25	MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions	58
A-1	Document Revision History	59

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List of Tables

SPRUE30B –September 2006

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Contents Users Guide Submit Documentation Feedback Contents Appendix a List of Figures List of Tables Read This First Trademarks Features Functional Block DiagramPurpose of the Peripheral Supported Use Case Statement Industry Standards Compliance StatementMMC/SD Controller Interface Diagram MMC/SD Controller Clocking Diagram Clock Control1 MMC/SD Mode Write Sequence Signal DescriptionsMMC/SD Controller Pins Used in Each Mode Protocol DescriptionsMMC/SD Mode Write Sequence 2 MMC/SD Mode Read SequencePortion Sequence Description CRC MMC/SD Mode Read SequenceData Flow in the Input/Output Fifo RD CMDFifo Operation Diagram Data Flow in the Data Registers Mmcdrr and Mmcdxr 1st 2nd 3rd 4th Mmcdrr or Mmcdxr registers Support byten =1st 2nd 3rd 4th Support byten = 1111 1110 Fifo Operation During Card Read Operation Edma ReadsCPU Reads Fifo Operation During Card Read Diagram Fifo Operation During Card Write Operation Edma WritesCPU Writes Fifo Operation During Card Write Diagram Reset Considerations InitializationInitialize the Time-Out Registers Mmctor and Mmctod Initializing the Clock Controller Registers MmcclkInitialize the Interrupt Mask Register Mmcim Initialize the Data Block Registers Mmcblen and MmcnblkMonitoring Activity in the MMC/SD Mode Determining Whether New Data is Available in MmcdrrChecking For a Data Transmit Empty Condition Interrupt Multiplexing Interrupt SupportInterrupt Events and Requests Description of MMC/SD Interrupt RequestsPower Management DMA Event SupportEmulation Considerations MMC Card Identification Procedure Card Identification OperationProcedures for Common Operations SD Card Identification Procedure MMC/SD Mode Single-Block Write Operation Using CPU MMC/SD Mode Single-Block Write Operation MMC/SD Mode Single-Block Write Operation Using the Edma MMC/SD Mode Single-Block Read Operation Using the CPUMMC/SD Mode Single-Block Read Operation Using Edma MMC/SD Mode Single-Block Read OperationMMC/SD Mode Multiple-Block Write Operation Using CPU MMC/SD Multiple-Block Write Operation MMC/SD Mode Multiple-Block Write Operation Using Edma MMC/SD Mode Multiple-Block Read Operation Using CPUMMC/SD Mode Multiple-Block Read Operation Using Edma MMC/SD Mode Multiple-Block Read OperationOffset Acronym Register Description MMC Control Register Mmcctl MMC Control Register Mmcctl Field DescriptionsBit Field Value Description Clken Clkrt MMC Memory Clock Control Register MmcclkMMC Memory Clock Control Register Mmcclk Field Descriptions ClkenMMC Status Register 0 MMCST0 MMC Status Register 0 MMCST0 Field DescriptionsBit Field Write-data CRC error Fifoful Fifoemp DAT3ST Drful Dxemp Clkstp Busy MMC Status Register 1 MMCST1MMC Status Register 1 MMCST1 Field Descriptions FifofulEtrndne Edated Edrrdy Edxrdy MMC Interrupt Mask Register MmcimMMC Interrupt Mask Register Mmcim Field Descriptions EtrndneMMC Response Time-Out Register Mmctor MMC Response Time-Out Register Mmctor Field DescriptionsTOR MMC Data Read Time-Out Register Mmctod MMC Data Read Time-Out Register Mmctod Field DescriptionsMMC Block Length Register Mmcblen MMC Block Length Register Mmcblen Field DescriptionsBlen MMC Number of Blocks Register Mmcnblk Field Descriptions MMC Number of Blocks Register MmcnblkMMC Number of Blocks Counter Register Mmcnblc NblkMMC Data Receive Register Mmcdrr Field Descriptions MMC Data Receive Register MmcdrrMMC Data Transmit Register Mmcdxr MMC Data Transmit Register Mmcdxr Field DescriptionsDmatrig MMC Command Register MmccmdMMC Command Register Mmccmd Field Descriptions Dclr Initck Wdatx Strmtp Dtrw Rspfmt Bsyexp PplenStream enable Bit Position Command Register DescriptionCRC7 Argh MMC Argument Register MmcarghlMMC Argument Register Mmcarghl Field Descriptions ArglMMC Response Registers MMCRSP0-MMCRSP7 Bit Position of Response Register R1, R3, R4, R5, or R6 Response 48 BitsR2 Response 136 Bits MMCRSP4-0MMC Data Response Register Mmcdrsp MMC Command Index Register MmccidxMMC Command Index Register Mmccidx Field Descriptions MMC Data Response Register Mmcdrsp Field DescriptionsAccwd Fifolev Fifodir Fiforst MMC Fifo Control Register MmcfifoctlMMC Fifo Control Register Mmcfifoctl Field Descriptions AccwdTable A-1. Document Revision History Reference Additions/Modifications/DeletionsAppendix a Important Notice