Index
%
%S references
OVR_PRE not available with Redundancy CPUs,
A
Active unit
defined,
Appendix A
IC690CBL714A
B
Background Window time,
different for redundancy CPUs,
Backup CPU
validating the logic solution,
Backup Unit
defined,
switching control to,
commanding from program,
validating the input scan,
Base sweep time
CGR772,
CGR935,
Battery connectors, 2-4
Bus Controller, Genius
configuring,
installation requirements,
installing dual GBCs at same end of bus,
switching,
Bus Receiver Module
connectors,
Bus termination,
Bus Transmitter Module
configuring,
Bus, Genius
C
C debugger,
different for redundancy CPUs,
Cable
Checksum,
Checksum, program memory,
terminating,
Compatibility
CGR935 and CPU780,
Configurable faults,
Configuration
connection for programmer,
Constant Sweep mode,
Control programming software,
summarized,
CPU architecture,
CPU failure,
CPU LEDs
ENabled,
MEMory PROTECT,
OK,
P1, Port 1,
P2, Port 2,
P3, Port 3,
RUN,
CPU mode switch
positions and commands,
CPU Modes,
CPU Redundancy
defined,
CPU Redundancy modules
IC697CGR772,
IC697CGR935,
CPU Redundancy, duplex,
defined,
D
Data Transfer,
from backup to active unit,
outputs,
Dual Bus
defined,
Duplex CPU Redundancy,