Albatron Technology ARM11/Cortex-A8 user manual Supported Flash Memories

Page 36

bdiGDB for GNU Debugger, BDI2000 (ARM11/Cortex-A8)

User Manual 36

Supported Flash Memories:

There are currently 3 standard flash algorithm supported. The AMD, Intel and Atmel AT49 algorithm. Almost all currently available flash memories can be programmed with one of this algorithm. The flash type selects the appropriate algorithm and gives additional information about the used flash.

For 8bit only flash:

AM29F (MIRROR), I28BX8, AT49

For 8/16 bit flash in 8bit mode:

AM29BX8 (MIRRORX8), I28BX8 (STRATAX8), AT49X8

For 8/16 bit flash in 16bit mode:

AM29BX16 (MIRRORX16), I28BX16 (STRATAX16), AT49X16

For 16bit only flash:

AM29BX16, I28BX16, AT49X16

For 16/32 bit flash in 16bit mode:

AM29DX16

For 16/32 bit flash in 32bit mode:

AM29DX32

For 32bit only flash:

M58X32

Some newer Spansion MirrorBit flashes cannot be programmed with the MIRRORX16 algorithm be- cause of the used unlock address offset. Use S29M32X16 for these flashes.

The AMD and AT49 algorithm are almost the same. The only difference is, that the AT49 algorithm does not check for the AMD status bit 5 (Exceeded Timing Limits).

Only the AMD and AT49 algorithm support chip erase. Block erase is only supported with the AT49 algorithm. If the algorithm does not support the selected mode, sector erase is performed. If the chip does not support the selected mode, erasing will fail. The erase command sequence is different only in the 6th write cycle. Depending on the selected mode, the following data is written in this cycle (see also flash data sheets): 0x10 for chip erase, 0x30 for sector erase, 0x50 for block erase.

To speed up programming of Intel Strata Flash and AMD MirrorBit Flash, an additional algorithm is implemented that makes use of the write buffer. This algorithm needs a workspace, otherwise the standard Intel/AMD algorithm is used.

The following table shows some examples:

Flash

x 8

x 16

x 32

Chipsize

 

 

 

 

 

Am29F010

AM29F

-

-

0x020000

 

 

 

 

 

Am29F800B

AM29BX8

AM29BX16

-

0x100000

 

 

 

 

 

Am29DL323C

AM29BX8

AM29BX16

-

0x400000

 

 

 

 

 

Am29PDL128G

-

AM29DX16

AM29DX32

0x01000000

 

 

 

 

 

Intel 28F032B3

I28BX8

-

-

0x400000

 

 

 

 

 

Intel 28F640J3A

STRATAX8

STRATAX16

-

0x800000

 

 

 

 

 

Intel 28F320C3

-

I28BX16

-

0x400000

 

 

 

 

 

AT49BV040

AT49

-

-

0x080000

 

 

 

 

 

AT49BV1614

AT49X8

AT49X16

-

0x200000

 

 

 

 

 

M58BW016BT

-

-

M58X32

0x200000

 

 

 

 

 

SST39VF160

-

AT49X16

-

0x200000

 

 

 

 

 

Am29LV320M

MIRRORX8

MIRRORX16

-

0x400000

 

 

 

 

 

© Copyright 1997-2007 by ABATRON AG Switzerland

V 1.04

Page 35 Page 37
Image 36
Page 35 Page 37
Contents BdiGDB Installation Using bdiGDBIntroduction BDI2000 BDI ConfigurationTroubleshooting Maintenance Trademarks AppendicesIntroduction BDI2000BDI Configuration Installation Connecting the BDI2000 to TargetFor BDI Main / Target a connector signals see table on next BDI Main / Target a Connector Signals Jtag Test ResetChanging Target Processor Type For Target B connector signals see table on next Adaptive ClockingBDI Target B Connector Signals Returned Jtag Test ClockPlease switch on the system in the following sequence External power supply Target systemPower Supply from Target System 142Status LED «MODE» Built in LED indicates the following BDI statesRS232 Connector BASE-T Connector Ethernet communicationPC Host Name DescriptionInstallation of the Configuration Software Overview of an installation / configuration processActivating Bootp Build the setup tool Load/Update the BDI firmware/logic1 Configuration with a Linux / Unix host Following the steps to bring-up a new BDI2000Check configuration and exit loader mode Transmit the initial configuration parametersfile name without any path For more information about Tftp use man tftpd2 Configuration with a Windows host Ory / programmable logicRecover procedure Reassemble the unit as described in Appendix «Maintenance»Testing the BDI2000 to host connection Tftp server for Windows NTUsing bdiGDB Principle of operationConfiguration File Part Init BdiGDB for GNU Debugger, BDI2000 ARM11/Cortex-A8 Using a startup program to initialize the target system ROM on the target, select ROM as the formatFormat COFF, SREC, AOUT, BIN, ELF or ROM Example Format CoffPart Target Cputype ARM1136None PushpullHalt StopRUN LoadonlySoft HardBreakmode Hard CoreDaisy chained Jtag devices Low level Jtag scan chain configuration Part Host Prompt ARM11 Dump filenamePart Flash BLOCK, CHIP, Unlock Supported Flash Memories AM29BX8 MIRRORX8, I28BX8 STRATAX8, AT49X8Or use the Telnet unlock command Tor. In other words, this is the size of one sector in bytesPart Regs Example for a register definition Entry in the configuration fileRegister definition file Target setup Connecting to the targetDebugging with GDB GDB monitor command Breakpoint HandlingTarget serial I/O via BDI Target DCC I/O via BDI Telnet Interface Command list DumpCPxx Registers Some examples CP15 ID register CRn = 0, opcode2 =CP15 Cache Type CRn = 0, opcode2 = CP15 Invalidate I cache line CRn = 7, opcode2 = 1, CRm =Multi-Core Support Specifications BASE-TEnvironmental notice Declaration of Conformity CEWarranty Troubleshooting Problemfirmware can not be loaded Possible reasonsMaintenance Unplug the cablesReinstallation Trademarks All trademarks are property of their respective holders
Top Page Image Contents