Albatron Technology ARM11/Cortex-A8 user manual Command list, Dump

Page 45

bdiGDB for GNU Debugger, BDI2000 (ARM11/Cortex-A8)

User Manual

45

 

 

 

 

3.4.1 Command list

 

 

 

"MD

 

[<address>] [<count>]

display target memory as word (32bit)",

 

 

"MDH

 

[<address>] [<count>]

display target memory as half word (16bit)",

 

 

"MDB

 

[<address>] [<count>]

display target memory as byte (8bit)",

 

 

"DUMP

<addr> <size> [<file>]

dump target memory to a file",

 

 

"MM

 

<addr> <value> [<cnt>]

modify word(s) (32bit) in target memory",

 

 

"MMH

 

<addr> <value> [<cnt>]

modify half word(s) (16bit) in target memory",

 

 

"MMB

 

<addr> <value> [<cnt>]

modify byte(s) (8bit) in target memory",

 

 

"MT

 

<addr> <count>

memory test",

 

 

"MC

 

[<address>] [<count>]

calculates a checksum over a memory range",

 

 

"MV

 

 

verifies the last calculated checksum",

 

 

"RD

 

[<name>]

display general purpose or user defined register",

 

"RDUMP [<file>]

dump all user defined register to a file",

 

 

"RDALL

 

display all ARM registers ",

 

 

"RDCP

[<cp>] <number>

display CP register, default is CP15",

 

 

"RDFP

 

display floating point register",

 

 

"RM

 

{<nbr> <name>} <value> modify general purpose or user defined register",

 

"RMCP

[<cp>] <number><value> modify CP register, default is CP15",

 

 

"DTLB <from> [<to>]

display Data TLB entries",

 

 

"ITLB <from> [<to>]

display Inst TLB entries",

 

 

"LTLB <from> [<to>]

ARM11: display Lockable Main TLB entries",

 

 

"ATLB <from> [<to>]

ARM11: display Set-Associative Main TLB entries",

 

"DTAG

<from> [<to>]

display L1 Data Cache Tag(s) ",

 

 

"ITAG

<from> [<to>]

display L1 Inst Cache Tag(s) ",

 

 

"BOOT

 

reset the BDI and reload the configuration",

 

 

"RESET [HALT RUN [time]]

reset the target system, change startup mode",

 

 

"GO

 

[<pc>]

set PC and start current core",

 

 

"GO

 

<n> <n> [<n>[<n>]]

start multiple cores in requested order",

 

 

"TI

 

[<pc>]

single step an instruction",

 

 

"HALT

[<n>[<n>[<n>[<n>]]]]

force core(s) to debug mode (n = core number)",

 

 

"BI

<addr>

set instruction breakpoint",

 

 

"CI

[<id>]

clear instruction breakpoint(s)",

 

 

"BD

[RW] <addr>

set data watchpoint (32bit access)",

 

 

"BDH [RW] <addr>

set data watchpoint (16bit access)",

 

 

"BDB [RW] <addr>

set data watchpoint ( 8bit access)",

 

 

"CD [<id>]

clear data watchpoint(s)",

 

 

"INFO

 

display information about the current state",

 

 

"LOAD

[<offset>] [<file> [<format>]] load program file to target memory",

 

 

"VERIFY [<offset>] [<file> [<format>]] verify a program file to target memory",

 

"PROG

[<offset>] [<file> [<format>]] program flash memory",

 

 

"

 

<format> : SREC, BIN, AOUT, ELF or COFF",

 

 

"ERASE

[<address> [<mode>]]

erase a flash memory sector, chip or block",

 

 

"

 

<mode> :

CHIP, BLOCK or SECTOR (default is sector)",

 

 

"ERASE

<addr> <step> <count>

erase multiple flash sectors",

 

 

"UNLOCK [<addr> [<delay>]]

unlock a flash sector",

 

 

"UNLOCK <addr> <step> <count>

unlock multiple flash sectors",

 

 

"FLASH

<type> <size> <bus>

change flash configuration",

 

 

"FENA

<addr> <size>

enable autoamtic programming to flash memory",

 

 

"FDIS

 

disable autoamtic programming to flash memory",

 

 

"DELAY

<ms>

delay for a number of milliseconds",

 

 

"MEMACC {CORE AHB [<hprot>]} Cortex-A8: select memory access mode",

 

 

"SELECT <core>

change the current core",

 

 

"HOST

<ip>

change IP address of program file host",

 

 

"PROMPT <string>

defines a new prompt string",

 

 

"CONFIG

display or update BDI configuration",

 

 

"CONFIG <file> [<hostIP> [<bdiIP> [<gateway> [<mask>]]]]",

 

 

"HELP

 

display command list",

 

 

"QUIT

 

terminate the Telnet session"

 

 

 

 

 

 

 

 

 

 

 

 

 

 

© Copyright 1997-2007 by ABATRON AG Switzerland

V 1.04

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Contents BdiGDB Using bdiGDB InstallationIntroduction BDI2000 BDI ConfigurationAppendices Troubleshooting Maintenance TrademarksBDI2000 IntroductionBDI Configuration Installation Connecting the BDI2000 to TargetFor BDI Main / Target a connector signals see table on next Jtag Test Reset BDI Main / Target a Connector SignalsChanging Target Processor Type Adaptive Clocking For Target B connector signals see table on nextReturned Jtag Test Clock BDI Target B Connector SignalsExternal power supply Target system Please switch on the system in the following sequence142 Power Supply from Target SystemBuilt in LED indicates the following BDI states Status LED «MODE»RS232 Connector Ethernet communication BASE-T ConnectorPC Host Name DescriptionInstallation of the Configuration Software Overview of an installation / configuration processActivating Bootp Load/Update the BDI firmware/logic Build the setup tool1 Configuration with a Linux / Unix host Following the steps to bring-up a new BDI2000Transmit the initial configuration parameters Check configuration and exit loader modefile name without any path For more information about Tftp use man tftpdOry / programmable logic 2 Configuration with a Windows hostReassemble the unit as described in Appendix «Maintenance» Recover procedureTftp server for Windows NT Testing the BDI2000 to host connectionPrinciple of operation Using bdiGDBConfiguration File Part Init BdiGDB for GNU Debugger, BDI2000 ARM11/Cortex-A8 ROM on the target, select ROM as the format Using a startup program to initialize the target systemFormat COFF, SREC, AOUT, BIN, ELF or ROM Example Format CoffCputype ARM1136 Part TargetNone PushpullStop HaltRUN LoadonlyHard SoftBreakmode Hard CoreDaisy chained Jtag devices Low level Jtag scan chain configuration Part Host Dump filename Prompt ARM11Part Flash BLOCK, CHIP, Unlock AM29BX8 MIRRORX8, I28BX8 STRATAX8, AT49X8 Supported Flash MemoriesTor. In other words, this is the size of one sector in bytes Or use the Telnet unlock commandPart Regs Example for a register definition Entry in the configuration fileRegister definition file Target setup Connecting to the targetDebugging with GDB Breakpoint Handling GDB monitor commandTarget serial I/O via BDI Target DCC I/O via BDI Telnet Interface Dump Command listSome examples CP15 ID register CRn = 0, opcode2 = CPxx RegistersCP15 Cache Type CRn = 0, opcode2 = CP15 Invalidate I cache line CRn = 7, opcode2 = 1, CRm =Multi-Core Support BASE-T SpecificationsDeclaration of Conformity CE Environmental noticeWarranty Problem Troubleshootingfirmware can not be loaded Possible reasonsUnplug the cables MaintenanceReinstallation All trademarks are property of their respective holders Trademarks