Albatron Technology ARM11/Cortex-A8 user manual Low level Jtag scan chain configuration

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bdiGDB for GNU Debugger, BDI2000 (ARM11/Cortex-A8)

User Manual 31

Low level JTAG scan chain configuration:

Sometimes it is necessary to configure the test access port (TAP) of the target before the ARM debug interface is visible and accessible in the usual way. The BDI supports this configuration in a very ge- neric way via the SCANINIT and SCANPOST configuration commands. Both accept a string that de- fines the JTAG sequences to execute. The following example shows how to use these commands:

; Configure

ICEPick module to make

ARM926 TAP visible

SCANINIT

t1:w1000:t0:w1000:

;toggle TRST

SCANINIT

i6=07:d8=89:i6=02:

;connect and select router

SCANINIT

d32=81000082:

;set IP control

SCANINIT

d32=a018206f:

;configure TAP0

SCANINIT

d32=a018216f:cl5:

;enable TAP0, clock 5 times in RTI

SCANINIT

i10=ffff

;scan bypass

;

 

 

;Between SCANINIT and SCANPOST the ARM ICEBreaker is configured

;and the DBGRQ bit in the ARM debug control register is set.

;

 

 

SCANPOST

i10=002f:

;IP(router) - ARM(bypass)

SCANPOST

d33=0102000106:

;IP control = SysReset

SCANPOST

i10=ffff

;scan bypass

The following low level JTAG commands are supported in the string. Use ":" between commands.

I<n>=<...

b2b1b0>

write IR, b0 is first scanned

D<n>=<...

b2b1b0>

write DR, b0 is first scanned

 

 

n : the number of bits 1..256

 

 

bx : a data byte, two hex digits

W<n>

 

wait for n (decimal) micro seconds

T1

 

assert TRST

T0

 

release TRST

R1

 

assert RESET

R0

 

release RESET

CH<n>

 

clock TCK n (decimal) times with TMS high

CL<n>

 

clock TCK n (decimal) times with TMS low

The following diagram shows the parts of the standard reset sequence that are replaced with the SCAN string. Only the appropriate part of the reset sequence is replaced. If only a SCANINIT string is defined, then the standard "post" sequence is still executed.

If (reset mode == hard) Assert reset

Toggle TRST

If (reset mode == hard) Delay for reset time

Execute SCANINIT string

Check if Bypass register(s) present

Read and display ID code

Check if debug module is accessible

If (startup == reset) catch reset exception

If (reset mode == hard) Release reset

Wait until reset is really release

Delay for wake-up time

Execute SCANPOST string

© Copyright 1997-2007 by ABATRON AG Switzerland

V 1.04

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Contents BdiGDB BDI2000 BDI Configuration InstallationUsing bdiGDB IntroductionAppendices Troubleshooting Maintenance TrademarksBDI2000 IntroductionBDI Configuration Connecting the BDI2000 to Target InstallationFor BDI Main / Target a connector signals see table on next Jtag Test Reset BDI Main / Target a Connector SignalsChanging Target Processor Type Adaptive Clocking For Target B connector signals see table on nextReturned Jtag Test Clock BDI Target B Connector SignalsExternal power supply Target system Please switch on the system in the following sequence142 Power Supply from Target SystemBuilt in LED indicates the following BDI states Status LED «MODE»RS232 Connector Name Description BASE-T ConnectorEthernet communication PC HostOverview of an installation / configuration process Installation of the Configuration SoftwareActivating Bootp Following the steps to bring-up a new BDI2000 Build the setup toolLoad/Update the BDI firmware/logic 1 Configuration with a Linux / Unix hostFor more information about Tftp use man tftpd Check configuration and exit loader modeTransmit the initial configuration parameters file name without any pathOry / programmable logic 2 Configuration with a Windows hostReassemble the unit as described in Appendix «Maintenance» Recover procedureTftp server for Windows NT Testing the BDI2000 to host connectionPrinciple of operation Using bdiGDBConfiguration File Part Init BdiGDB for GNU Debugger, BDI2000 ARM11/Cortex-A8 Format Coff Using a startup program to initialize the target systemROM on the target, select ROM as the format Format COFF, SREC, AOUT, BIN, ELF or ROM ExamplePushpull Part TargetCputype ARM1136 NoneLoadonly HaltStop RUNCore SoftHard Breakmode HardDaisy chained Jtag devices Low level Jtag scan chain configuration Part Host Dump filename Prompt ARM11Part Flash BLOCK, CHIP, Unlock AM29BX8 MIRRORX8, I28BX8 STRATAX8, AT49X8 Supported Flash MemoriesTor. In other words, this is the size of one sector in bytes Or use the Telnet unlock commandPart Regs Entry in the configuration file Example for a register definitionRegister definition file Connecting to the target Target setupDebugging with GDB Breakpoint Handling GDB monitor commandTarget serial I/O via BDI Target DCC I/O via BDI Telnet Interface Dump Command listCP15 Invalidate I cache line CRn = 7, opcode2 = 1, CRm = CPxx RegistersSome examples CP15 ID register CRn = 0, opcode2 = CP15 Cache Type CRn = 0, opcode2 =Multi-Core Support BASE-T SpecificationsDeclaration of Conformity CE Environmental noticeWarranty Possible reasons TroubleshootingProblem firmware can not be loadedUnplug the cables MaintenanceReinstallation All trademarks are property of their respective holders Trademarks