HP 8000 tower manual Parallel Interface Support, Standard Parallel Port Mode

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5.4Parallel Interface Support

Input/Output Interfaces

5.4Parallel Interface Support

The SFF and CMT form factors include a system board header (J50) that supports an optional parallel bracket/cable assembly that provides a parallel interface for a peripheral device such as a printer. The parallel interface supports bi-directional 8-bit parallel data transfers with a peripheral device. The parallel interface supports three main modes of operation:

■Standard Parallel Port (SPP) mode

■Enhanced Parallel Port (EPP) mode

■Extended Capabilities Port (ECP) mode

These three modes (and their submodes) provide complete support as specified for an IEEE 1284 parallel port.

5.4.1 Standard Parallel Port Mode

The Standard Parallel Port (SPP) mode uses software-based protocol and includes two sub-modes of operation, compatible and extended, both of which can provide data transfers up to 150 KB/s. In the compatible mode, CPU write data is simply presented on the eight data lines. A CPU read of the parallel port yields the last data byte that was written.

5.4.2 Enhanced Parallel Port Mode

In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to EPP timing. A watchdog timer is used to prevent system lockup.

5.4.3 Extended Capabilities Port Mode

The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or programmed I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with ECP mode. If compatible, then ECP mode can be used.

The ECP mode includes several sub-modes as determined by the Extended Control register. Two submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO is cleared and not used, and DMA and RLE are inhibited.

 

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Contents December Technical Reference GuideHP Compaq 8000 Elite Series Business Desktop Computers Document Part NumberHP Compaq 8000 Elite Series Business Desktop Computers Technical Reference GuideFirst Edition December Document Part Number 1 Introduction Contents2 System Overview 4 System Support 3 Processor/Memory Subsystem5 Input/Output Interfaces 6 Integrated Graphics Subsystem 7 Power and Signal DistributionA Error Messages and Codes Index 8 SYSTEM BIOS1.1.1 Online Viewing Introduction1.1 About this Guide 1.2 Additional Information Sources1.4.2 Values 1.3 Serial Number1.4 Notational Conventions 1.4.1 Special NoticesAbbreviation 1.5 Common Acronyms and AbbreviationsAcronyms and Abbreviations Acronym orTable 1-1 Continued Abbreviation Table 1-1 ContinuedAcronyms and Abbreviations Acronym orAbbreviation Table 1-1 ContinuedAcronyms and Abbreviations Acronym orAbbreviation Table 1-1 ContinuedAcronyms and Abbreviations Acronym orAbbreviation Table 1-1 ContinuedAcronyms and Abbreviations Acronym orAbbreviation 1-10 2.1 Introduction System Overview2.2 Features USDT Feature Differences by Form FactorArchitectural Differences by Form Factor 2.3 System ArchitectureTechnical Reference Guide 2.3.2 Chipset 2.3.1 Intel Processor SupportChipset Components and Functionality 2.3.4 System Memory 2.3.3 Support ComponentsSupport Component Functions 2.3.8 Network Interface Controller 2.3.5 Mass Storage2.3.6 Serial Interface 2.3.7 Universal Serial Bus Interface2.3.10 Audio Subsystem 2.3.9 Graphics SubsystemIntegrated Graphics Subsystem Statistics 2.3.11 HP ProtectTools Embedded Security 2.4 SpecificationsEnvironmental Specifications Factory Configuration Physical Specifications Power Supply Electrical Specifications2-12 3.1 Introduction Processor/Memory Subsystem3.2.1 Intel Processor Overview 3.2 Intel ProcessorsSupported Processors partial listing 3.2.2 Processor Changing/Upgrading3.3 Memory Subsystem 3.3.2 Memory Mapping and Pre-allocation 3.3.1 Memory UpgradingMemory Socket Loading Expansion Area Figure 3-2. System Memory Map for maximum of 8 gigabytesBase Memory 4.2.1 PCI 2.3 Bus Operation System Support4.1 Introduction 4.2 PCI Bus OverviewPCI Bus PCI Component Configuration AccessWired to System SupportPCI Bus Mastering Devices 4.2.2 PCI Express Bus OperationSoftware/Driver Layer Transaction Protocol LayerLink Layer 4.2.5 PCI Power Management Support4.2.3 Option ROM Mapping 4.2.4 PCI InterruptsFigure 4-2. 32-bit, 5.0-volt PCI 2.3 Bus Connector 4.2.6 PCI ConnectorsPCI 2.3 Connector PCI 2.3 Bus Connector PinoutPCIe Bus Connector Pinout PCIe ConnectorsFigure 4-3. PCIe Bus Connectors APIC Mode 4.3 System Resources4.3.1 Interrupts 8259 ModePCI Interrupt Distribution 4.3.2 Direct Memory Access4.4.1 Clearing CMOS 4.4 Real-Time Clock and Configuration MemoryConfiguration Memory CMOS Map 4.5 System Management4.4.2 Standard CMOS Locations 4.5.1 Security FunctionsI/O Interface Security Power-On / Setup PasswordSetup Password Cable Lock ProvisionSmart Cover Lock Optional 4.5.2 Power ManagementACPI Wake-Up Events 4.5.4 Thermal Sensing and Cooling 4.5.3 System StatusSystem Operational Status LED Indications 4.6.1 System I/O Map 4.6 Register Map and Miscellaneous FunctionsI/O Port System I/O MapFunction ICH10 Functions 4.6.2 GPIO FunctionsSIO Controller Functions 5.1 Introduction Input/Output Interfaces5.2.1 SATA interface 5.2 SATA/eSATA Interfaces5.2.2 eSATA interface DB-9 Serial Connector Pinout 5.3 Serial Interface5.4.3 Extended Capabilities Port Mode 5.4 Parallel Interface Support5.4.1 Standard Parallel Port Mode 5.4.2 Enhanced Parallel Port ModeDB-25 Parallel Connector Pinout 5.4.4 Parallel Interface Connectore w q - 9 8 7 6 5 4 3 2 1 g f d s a p o i u y t r 5.5.1 Keyboard Interface Operation 5.5 Keyboard/Pointing Device Interface5.5.2 Pointing Device Interface Operation 5.5.3 Keyboard/Pointing Device Interface ConnectorKeyboard/Pointing Device Connector Pinout 5.6 Universal Serial Bus Interface 5.6.1 USB ConnectorUSB Color Code 5.6.2 USB Cable DataUSB Connector Pinout USB Cable Length DataFigure 5-8. Audio Subsystem Functional Block Diagram 5.7 Audio Subsystem5.7.2 HD Audio Link Bus 5.7.1 HD Audio Controller5.7.3 Audio Multistreaming The specifications for the HD Audio subsystem are listed in Table 5.7.4 Audio SpecificationsHD Audio Subsystem Specifications 5.8 Network Interface Controller 5.8.1 Wake-On-LAN Support 5.8.3 Power Management Support5.8.2 Alert Standard Format Support 5.8.5 NIC Specifications 5.8.4 NIC ConnectorTable 5-11. NIC Specifications 6.1 Introduction Integrated Graphics Subsystem6.2 Functional Description GMA 4500 Memory Allocation SDRAM InstalledMaximum Memory Allocation 6.3 Display Modes 6.4 Upgrading 6.5.1 Analog Monitor Connector 6.5 Monitor ConnectorsFigure 6-3. DisplayPort Connector, as viewed from rear of chassis 6.5.2 DisplayPort ConnectorTechnical Reference Guide 7.2 USDT Power Distribution Power and Signal Distribution7.1 Introduction Figure 7-2. SFF/CMT Power Distribution and Cabling, Block Diagram 7.3 SFF/CMT Power DistributionTable 7-1 lists the specifications of the external supply USDT 135-Watt Power Supply Unit SpecificationsCMT 320-Watt Power Supply Unit Specifications SFF 240-Watt Power Supply Unit Specifications7.4.1 Power Button 7.4 Power ControlPre-video memory error. Incompatible or incorrectly seated Power LED IndicationsPower LED Power failure power supply is overloaded. Check storageWake-On-LAN 7.5 Power Management7.4.2 Wake Up Events Power Management EventState System Power StatesPower PowerComponent function 7.6 Signal DistributionSystem Board Connector, Indicator, and Switch Designations DesignatorTable 7-7. Continued Figure 7-5 shows pinouts of headers used on the sytem boardsFigure 7-3. System Board Header Pinouts 7-10 8.1 Introduction System BIOS8.2.1 Upgrading 8.2 ROM Flashing8.2.2 Changeable Splash Screen 8.3.3 Memory Detection and Configuration 8.3 Boot Functions8.3.1 Boot Device Order 8.3.2 Network Boot F12 Support8.3.4 Boot Error Codes 8.4 Client Management Functions 8.4.2 Temperature Status 8.4.1 System ID and ROM TypeSystem ID Numbers SMBIOS Functions 8.5 SMBIOS8.7 Management Engine Functions 8.6 USB Legacy SupportA.2 Beep/Power LED Codes Error Messages and CodesA.1 Introduction Error Messages and Codes A.3 Power-On Self Test POST Messages1796-SATA Cabling Error Power-On Self Test POST MessagesError Message 1794--Inaccessible device attached to SATA1801-Microcode Patch Error Error Messages and Codes A.4 System Error MessagesMemory Error Messages A.5 Memory Error MessagesTable A-4 Message A.6 Keyboard Error MessagesMemory Error Messages Table A-4. ContinuedInt. test, LpBk. test., and cntrl. register failed A.7 Printer Error MessagesA.8 Video Graphics Error Messages Int. test, LpBk. test., and data register failedA.9 Diskette Drive Error Messages Table A-9 Serial Interface Error Messages A.10 Serial Interface Error MessagesTable A-10 Modem Communications Error Messages A.11 Modem Communications Error MessagesA.12 System Status Error Messages Cntlr. failed to deallocate bad sectors A.13 Hard Drive Error Messagesxx = 00, Hard drive ID test xx = 01, Hard drive format test A.14 Hard Drive Error Messages Lightpen graphics test failed, no resp A.15 Video Graphics Error MessagesA.16 Audio Error Messages EGA Mono. graphics mode test failedA.18 Network Interface Error Messages A.17 DVD/CD-ROM Error MessagesMessage A.19 SCSI Interface Error Messages 65xx-xx, 66xx-xxProbable Cause A.20 Pointing Device Interface Error Messages 8601-xx A-20 Numerics Index
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