Texas Instruments TMS320DM646X DMSOC manuals

64 pages408.81 Kb

Preface
6Read This First
- About This Manual
- Notational Conventions
- Related Documentation From Texas Instruments
- User's Guide
8Asynchronous External Memory Interface (EMIF)
- 1 Introduction
- 1.1 Purpose of the Peripheral
- 1.2 Features
- 91.3 Functional Block Diagram
- 2 Architecture
- 2.1 Clock Control
- 2.2 EMIF Requests
- 102.3 Signal Descriptions
- 2.4 Pin Multiplexing
- 2.5 Asynchronous Controller and Interface
  - 13Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued)
  - Table 4. Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)
  - Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR)
  - Table 6. Description of the EMIF Interrupt Mast Clear Register (EIMCR)
  - 15Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode
  - NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.
  - 16Table 8. Asynchronous Write Operation in Normal Mode
  - 17Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode
  - 19Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode
  - NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.
  - 20Table 10. Asynchronous Write Operation in Select Strobe Mode
  - 21Figure 7. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode
- 303 Use Cases
- 3.1 Interfacing to Asynchronous SRAM (ASRAM)
  - 32Figure 12. Timing Waveform of an ASRAM Read
  - 35Figure 14. Timing Waveform of an ASRAM Read with PCB Delays
  - 36W_STROBE wtWP(m) tcyc *1
  - W_SETUP )W_STROBE wmaxtEM_A )tAW(m) *tEM_WE t cyc , t EM_D ) t DS (m) * t tcyc *1
  - W_HOLD wmaxtEM_WE )tWR(m) *tEM_A t cyc , t EM_WE ) t DH (m) * t tcyc *1
  - W_SETUP )W_STROBE )W_HOLD wtWC(m) tcyc *3
  - Figure 15. Timing Waveform of an ASRAM Write with PCB Delays
- 393.2 Interfacing to NAND Flash
  - 43Figure 17. Timing Waveform of a NAND Flash Command Write
  - Figure 18. Timing Waveform of a NAND Flash Address Write
  - 44Figure 19. Timing Waveform of a NAND Flash Data Write
    - Use Cases
  - 45Table 29. NAND Flash Timing Requirements for HY27UA081G1M Example
- 484 Registers
  - Table 32. External Memory Interface (EMIF) Registers
- 494.1 Revision Code and Status Register (RCSR)
  - Table 33. Revision Code and Status Register (RCSR) Field Descriptions
- 504.2 Asynchronous Wait Cycle Configuration Register (AWCCR)
  - Figure 21. Asynchronous Wait Cycle Configuration Register (AWCCR)
  - Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions
  - 51Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued)
- 524.3 Asynchronous n Configuration Registers (A1CR-A4CR)
  - Table 35. Asynchronous nConfiguration Register (ACFGn) Field Descriptions
- 534.4 EMIF Interrupt Raw Register (EIRR)
  - Table 36. EMIF Interrupt Raw Register (EIRR) Field Descriptions
- 544.5 EMIF Interrupt Mask Register (EIMR)
  - Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions
  - 55Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued)
- 564.6 EMIF Interrupt Mask Set Register (EIMSR)
  - Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions
  - 57Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued)
- 584.7 EMIF Interrupt Mask Clear Register (EIMCR)
  - Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions
  - 59Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued)
- 604.8 NAND Flash Control Register (NANDFCR)
  - Table 40. NAND Flash Control Register (NANDFCR) Field Descriptions
- 614.9 NAND Flash Status Register (NANDFSR)
- 4.10 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC)
  - 62Figure 29. NAND Flash nECC Register (NANDECCn)
  - Table 42. NAND Flash nECC Register (NANDECCn) Field Descriptions
- 63Appendix A Revision History
  - 64IMPORTANT NOTICE