EMWAIT2 pin is used | Texas Instruments TMS320DM646X DMSOC instruction

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Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued)

Bit	Field	Value	Description

17-16	CS2_WAIT	0-3h	EM_WAIT[5:2] pin map for chip select 2. By default, the EM_WAIT[2] pin is used for chip select 2.
		0	EM_WAIT[2] pin is used.
		1h	EM_WAIT[3] pin is used.
		2h	EM_WAIT[4] pin is used.
		3h	EM_WAIT[5] pin is used.

15-8	Reserved	0	Reserved

7-0	MEWC	0-FFh	Maximum extended wait cycles. The EMIF will wait for a maximum of (MEWC + 1) × 16 clock cycles
			before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access.

SPRUEQ7C –February 2010	Asynchronous External Memory Interface (EMIF)	51
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Texas Instruments TMS320DM646X DMSOC manual EMWAIT2 pin is used

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Users Guide Submit Documentation Feedback Appendix a Revision History List of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral Features Functional Block Diagram Clock ControlEmif Requests Asynchronous Controller and Interface Signal DescriptionsEmif Pins Pin Multiplexing Emif Asynchronous Interface Interfacing to Asynchronous Memory Programmable Asynchronous Parameters Configuring the Emif for Asynchronous Accesses Description of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register Eimsr Time Interval Pin Activity in WE Strobe Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Asynchronous Read Operation in Normal Mode Timing Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal Mode Address Time Interval Pin Activity in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Asynchronous Read Operation in Select Strobe Mode EMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe Mode EMD Description of the Nand Flash Control Register Nandfcr Nand Flash ModeConfiguring for Nand Flash Mode Configuration For Nand Flash Driving CLE and ALE Connecting to Nand Flash Nand Data Read and Write via DMA Nand Read and Program Operations ECC Value for 8-Bit Nand Flash ECC Generation Nand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Monitor and Control Bit Fields Interrupt SupportEmif Interrupt Interrupt Events Emulation Considerations Power ManagementInterrupt Multiplexing Program Execution Interfacing to Asynchronous Sram Asram Connecting to Asram Asram Input Timing Requirement for a Read Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Emif Input Timing Requirements Asram Input Timing Requirements for a Write Timing Waveform of an Asram Read Timing Waveform of an Asram Write Write Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Parameter Description Read Access Timing Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Asram Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Emif Timing Requirements for TC5516100FT-12 Example 27 12 5 Rsetup Rstrobe w Recommended Margins Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Margin Requirements Meeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Nand Flash mode for chip select Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Parameter Setting Offset Acronym Register Description External Memory Interface Emif Registers Revision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description WP3 Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 CS5WAIT CS4WAIT CS3WAIT CS2WAIT EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3 WR2 WR1 WR0 WRM3 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3 WRM2 WRM1 WRM0 AT bit in the Emif interrupt raw register Eirr WRMSET3 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3 WRMSET2 WRMSET1 WRMSET0 Bit in Eimcr WRMCLR3 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register Nandfcr Waitst Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register Nandfsr Field Descriptions P8O Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8E P4E P2E P1E Additions/Modifications/Deletions Document Revision History Products Applications DSPRfid