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Texas Instruments TMS320DM646X DMSOC manual Connecting to Nand Flash, Driving CLE and ALE

Models: TMS320DM646X DMSOC

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Architecture

2.5.6.2Connecting to NAND Flash

Figure 8 shows the EMIF external pins used to interface with a NAND Flash device. EMIF address lines are used to drive the NAND Flash device'scommand latch enable (CLE) and address latch enable (ALE) signals.

NOTE: The EMIF will not control the NAND Flash device'swrite protect pin. The write protect pin must be controlled outside of the EMIF.

Figure 8. EMIF to NAND Flash Interface

EMIF

CLE_EM_A[16] ALE_EM_A[17] EM_CS[n]

EM_WE

EM_OE EM_D[7:0] EM_WAIT[n]

NAND flash

CLE

ALE

CE

WE

OE

IO[7:0]

R/B

a) Connection to 8-bit NAND device

EMIF

CLE_EM_A[16]

ALE_EM_A[17] EM_CS[n] EM_WE EM_OE EM_D[15:0] EM_WAIT[n]

NAND flash

CLE

ALE

CE

WE

OE

IO[15:0]

R/B

b) Connection to 16-bit NAND device

2.5.6.3Driving CLE and ALE

As stated in Section 2.5.1, the EMIF always drives the least significant bit of a 32-bit word address on EM_A[0]. This functionality must be considered when attempting to drive the address lines connected to CLE and ALE to the appropriate state.

For example, if using EM_A[2] and EM_A[1] to connect to CLE and ALE, respectively, the following offsets should be chosen:

•00h to drive CLE and ALE low

•10h to drive CLE high and ALE low

•0Bh to drive CLE low and ALE high

These offsets should be added to the base address for the chip select space the NAND Flash device is connected to. For example, if the base address of the CS space the NAND Flash device is connected to is 4200 0000h, then the above list translates to the following memory-mapped addresses: 4200 0000h, 4200 0010h, and 4200 000Bh, respectively. Therefore, when attempting to drive CLE high and ALE low, the memory-mapped address of 4200 0010h would be written to.

SPRUEQ7C –February 2010	Asynchronous External Memory Interface (EMIF)	23
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Texas Instruments TMS320DM646X DMSOC manual Connecting to Nand Flash, Driving CLE and ALE

Contents

Users Guide Submit Documentation Feedback Appendix a Revision History List of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral Features Emif Requests Functional Block DiagramClock Control Asynchronous Controller and Interface Signal DescriptionsEmif Pins Pin Multiplexing Emif Asynchronous Interface Interfacing to Asynchronous Memory Programmable Asynchronous Parameters Configuring the Emif for Asynchronous Accesses Description of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register Eimsr Time Interval Pin Activity in WE Strobe Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Asynchronous Read Operation in Normal Mode Timing Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal Mode Address Time Interval Pin Activity in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Asynchronous Read Operation in Select Strobe Mode EMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe Mode EMD Description of the Nand Flash Control Register Nandfcr Nand Flash ModeConfiguring for Nand Flash Mode Configuration For Nand Flash Driving CLE and ALE Connecting to Nand Flash Nand Data Read and Write via DMA Nand Read and Program Operations ECC Value for 8-Bit Nand Flash ECC Generation Interfacing to a TI DSP HPI Nand Flash Status Register NandfsrInterfacing to a Non-CE Dont Care Nand Flash Data Bus Parking Extended Wait Mode and the Emwait PinReset and Initialization Considerations Interrupt Monitor and Control Bit Fields Interrupt SupportEmif Interrupt Interrupt Events Emulation Considerations Power ManagementInterrupt Multiplexing Program Execution Interfacing to Asynchronous Sram Asram Connecting to Asram Asram Input Timing Requirement for a Read Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Emif Input Timing Requirements Asram Input Timing Requirements for a Write Timing Waveform of an Asram Read Timing Waveform of an Asram Write Write Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Parameter Description Read Access Timing Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Asram Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Emif Timing Requirements for TC5516100FT-12 Example 27 12 5 Rsetup Rstrobe w Recommended Margins Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Margin Requirements Nand Flash Read Timing Requirements Meeting AC Timing Requirements for Nand FlashEmif Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Nand Flash Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MEmif Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Nand Flash mode for chip select Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Parameter Setting Offset Acronym Register Description External Memory Interface Emif Registers Bit Field Value Description Revision Code and Status Register RcsrRevision Code and Status Register Rcsr Field Descriptions WP3 Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 CS5WAIT CS4WAIT CS3WAIT CS2WAIT EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3 WR2 WR1 WR0 WRM3 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3 WRM2 WRM1 WRM0 AT bit in the Emif interrupt raw register Eirr WRMSET3 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3 WRMSET2 WRMSET1 WRMSET0 Bit in Eimcr WRMCLR3 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register Nandfcr Waitst Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register Nandfsr Field Descriptions P8O Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8E P4E P2E P1E Additions/Modifications/Deletions Document Revision History Rfid Products ApplicationsDSP