Texas Instruments TMS320DM646X DMSOC manual Emif Interrupt Mask Register Eimr, WRM3 WRM2 WRM1 WRM0

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4.5EMIF Interrupt Mask Register (EIMR)

Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used to monitor and clear the status of the EMIF’s hardware-generated interrupts. The main difference between the two registers is that when the bits in EIMR are set, an active-high pulse is sent to the CPU interrupt controller. Also, the bits in EIMR are only set to 1, if the associated interrupt has been enabled in the EMIF interrupt mask set register (EIMSR). The EIMR is shown in Figure 24 and described in Table 37.

		Figure 24. EMIF Interrupt Mask Register (EIMR)
31								16
			Reserved
				R-0
15								8
			Reserved
				R-0
7	6	5	4	3		2	1	0
	Reserved	WRM3	WRM2		WRM1	WRM0	Reserved	ATM
	R-0	R/W1C-0	R/W1C-0		R/W1C-0	R/W1C-0	R-0	R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions

Bit	Field	Value	Description
31-6	Reserved	0	Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
			value of 0.
5	WRM3		Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
			EM_WAIT[5] pin, provided that the WRMSET3 bit is set to 1 in the EMIF interrupt mask set register
			(EIMSR).
		0	Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
		1	Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM3 bit in
			the EMIF interrupt raw register (EIRR).
4	WRM2		Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
			EM_WAIT[4] pin, provided that the WRMSET2 bit is set to 1 in the EMIF interrupt mask set register
			(EIMSR).
		0	Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
		1	Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM2 bit in
			the EMIF interrupt raw register (EIRR).
3	WRM1		Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
			EM_WAIT[3] pin, provided that the WRMSET1 bit is set to 1 in the EMIF interrupt mask set register
			(EIMSR).
		0	Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
		1	Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM1 bit in
			the EMIF interrupt raw register (EIRR).
2	WRM0		Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
			EM_WAIT[2] pin, provided that the WRMSET0 bit is set to 1 in the EMIF interrupt mask set register
			(EIMSR).
		0	Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
		1	Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM0 bit in
			the EMIF interrupt raw register (EIRR).
1	Reserved	0	Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
			value of 0.

54	Asynchronous External Memory Interface (EMIF)	SPRUEQ7C –February 2010
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