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Texas Instruments TMS320DM646X DMSOC manual Interfacing to Asynchronous Memory

Models: TMS320DM646X DMSOC

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Architecture

2.5.1Interfacing to Asynchronous Memory

Figure 2 shows the EMIF'sexternal pins used in interfacing with an asynchronous device. Of special note is the connection between the EMIF and the external device'saddress bus. The EMIF address pin EM_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when interfacing to a 16-bit or 8-bit asynchronous device, the EM_BA[1] and EM_BA[0] pins provide the least-significant bits of the halfword or byte address, respectively. Figure 2 and Figure 3 show the mapping between the EMIF and the connected device'sdata and address pins for various programmed data bus widths. The data bus width may be configured in the asynchronous configuration register (ACFGn).

Figure 2. EMIF Asynchronous Interface

EMIF

EM_CS[5:2]

EM_WE

EM_OE

EM_RW

EM_WAIT[5:2]

EM_D[15:0]

EM_A[22:0]

EM_BA[1:0]

Figure 3. EMIF to 8-bit and 16-bit Memory Interfaces

EMIF

EM_D[7:0] EM_A[21:0] EM_BA[1:0]

8−bit asynchronous memory

DQ[7:0]

A[23:2]

A[1:0]

a) EMIF to 8-bit memory interface

EMIF

EM_D[15:0] EM_A[21:0] EM_BA[1]

16−bit asynchronous memory

DQ[15:0]

A[22:1]

A[0]

b) EMIF to 16-bit memory interface

SPRUEQ7C –February 2010	Asynchronous External Memory Interface (EMIF)	11
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Texas Instruments TMS320DM646X DMSOC manual Interfacing to Asynchronous Memory, Emif Asynchronous Interface

Contents

Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesEmif Requests Functional Block DiagramClock Control Asynchronous Controller and Interface Signal DescriptionsEmif Pins Pin MultiplexingEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrTime Interval Pin Activity in WE Strobe Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Asynchronous Read Operation in Normal ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Time Interval Pin Activity in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Asynchronous Read Operation in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Description of the Nand Flash Control Register Nandfcr Nand Flash ModeConfiguring for Nand Flash Mode Configuration For Nand FlashDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationInterfacing to a TI DSP HPI Nand Flash Status Register NandfsrInterfacing to a Non-CE Dont Care Nand Flash Data Bus Parking Extended Wait Mode and the Emwait PinReset and Initialization Considerations Interrupt Monitor and Control Bit Fields Interrupt SupportEmif Interrupt Interrupt EventsEmulation Considerations Power ManagementInterrupt Multiplexing Program ExecutionInterfacing to Asynchronous Sram Asram Connecting to AsramAsram Input Timing Requirement for a Read Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Emif Input Timing RequirementsAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Write Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Parameter Description Read AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Asram Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Emif Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Recommended Margins Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Margin RequirementsNand Flash Read Timing Requirements Meeting AC Timing Requirements for Nand FlashEmif Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Nand Flash Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MEmif Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Nand Flash mode for chip select Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Parameter SettingOffset Acronym Register Description External Memory Interface Emif RegistersBit Field Value Description Revision Code and Status Register RcsrRevision Code and Status Register Rcsr Field Descriptions WP3 Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 CS5WAIT CS4WAIT CS3WAIT CS2WAITEMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3 WR2 WR1 WR0WRM3 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3 WRM2 WRM1 WRM0AT bit in the Emif interrupt raw register Eirr WRMSET3 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3 WRMSET2 WRMSET1 WRMSET0Bit in Eimcr WRMCLR3 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrWaitst Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register Nandfsr Field DescriptionsP8O Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8E P4E P2E P1EAdditions/Modifications/Deletions Document Revision HistoryRfid Products ApplicationsDSP