WP3 WP2 WP1 WP0, CS5WAIT | Texas Instruments TMS320DM646X DMSOC

Registers

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4.2Asynchronous Wait Cycle Configuration Register (AWCCR)

The asynchronous wait cycle configuration register (AWCCR) is used to configure the parameters for extended wait cycles. Both the polarity of the EM_WAIT[5:2] pins and the maximum allowable number of extended wait cycles can be configured. the AWCCR is shown in Figure 21 and described in Table 34.

NOTE: The EW bit in the asynchronous configuration register (ACFGn) must be set to allow for the insertion of extended wait cycles.

Figure 21. Asynchronous Wait Cycle Configuration Register (AWCCR)

31	30	29	28		27	24	23	22	21	20	19	18	17	16
WP3	WP2	WP1	WP0			Reserved	CS5_WAIT		CS4_WAIT		CS3_WAIT		CS2_WAIT
R/W-1	R/W-1	R/W-1	R/W-1			R-0	R/W-3h		R/W-2h			R/W-1	R/W-0
15						8	7							0

			Reserved							MEWC
			R-0							R/W-80h
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions

Bit		Field	Value	Description

31		WP3		WAIT polarity bit. This bit defines the polarity of the EM_WAIT[5] pin.
			0	Insert wait cycles if EM_WAIT[5] pin is low.
			1	Insert wait cycles if EM_WAIT[5] pin is high.

30		WP2		WAIT polarity bit. This bit defines the polarity of the EM_WAIT[4] pin.
			0	Insert wait cycles if EM_WAIT[4] pin is low.
			1	Insert wait cycles if EM_WAIT[4] pin is high.

29		WP1		WAIT polarity bit. This bit defines the polarity of the EM_WAIT[3] pin.
			0	Insert wait cycles if EM_WAIT[3] pin is low.
			1	Insert wait cycles if EM_WAIT[3] pin is high.

28		WP0		WAIT polarity bit. This bit defines the polarity of the EM_WAIT[2] pin.
			0	Insert wait cycles if EM_WAIT[2] pin is low.
			1	Insert wait cycles if EM_WAIT[2] pin is high.

27-24		Reserved	0	Reserved

23-22		CS5_WAIT	0-3h	EM_WAIT[5:2] pin map for chip select 5. By default, the EM_WAIT[5] pin is used for chip select 5.
			0	EM_WAIT[2] pin is used.
			1h	EM_WAIT[3] pin is used.
			2h	EM_WAIT[4] pin is used.
			3h	EM_WAIT[5] pin is used.

21-20		CS4_WAIT	0-3h	EM_WAIT[5:2] pin map for chip select 4. By default, the EM_WAIT[4] pin is used for chip select 4.
			0	EM_WAIT[2] pin is used.
			1h	EM_WAIT[3] pin is used.
			2h	EM_WAIT[4] pin is used.
			3h	EM_WAIT[5] pin is used.

19-18		CS3_WAIT	0-3h	EM_WAIT[5:2] pin map for chip select 3. By default, the EM_WAIT[3] pin is used for chip select 3.
			0	EM_WAIT[2] pin is used.
			1h	EM_WAIT[3] pin is used.
			2h	EM_WAIT[4] pin is used.
			3h	EM_WAIT[5] pin is used.


50	Asynchronous External Memory Interface (EMIF)				SPRUEQ7C –February 2010
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Texas Instruments TMS320DM646X DMSOC manual Asynchronous Wait Cycle Configuration Register Awccr, WP3 WP2 WP1 WP0, CS5WAIT

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the Peripheral Emif Requests Functional Block DiagramClock Control Pin Multiplexing Signal DescriptionsEmif Pins Asynchronous Controller and Interface Interfacing to Asynchronous Memory Emif Asynchronous Interface Configuring the Emif for Asynchronous Accesses Programmable Asynchronous Parameters Description of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register Eimcr Asynchronous Read Operation in Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Time Interval Pin Activity in WE Strobe Mode Timing Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal Mode Address Asynchronous Read Operation in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Time Interval Pin Activity in Select Strobe Mode EMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe Mode EMD Configuration For Nand Flash Nand Flash ModeConfiguring for Nand Flash Mode Description of the Nand Flash Control Register Nandfcr Connecting to Nand Flash Driving CLE and ALE Nand Read and Program Operations Nand Data Read and Write via DMA ECC Generation ECC Value for 8-Bit Nand Flash Interfacing to a TI DSP HPI Nand Flash Status Register NandfsrInterfacing to a Non-CE Dont Care Nand Flash Data Bus Parking Extended Wait Mode and the Emwait PinReset and Initialization Considerations Interrupt Events Interrupt SupportEmif Interrupt Interrupt Monitor and Control Bit Fields Program Execution Power ManagementInterrupt Multiplexing Emulation Considerations Connecting to Asram Interfacing to Asynchronous Sram Asram Emif Input Timing Requirements Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Asram Input Timing Requirement for a Read Timing Waveform of an Asram Read Asram Input Timing Requirements for a Write Timing Waveform of an Asram Write Parameter Description Read Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Write Access Timing Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Emif Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example 27 12 5 Rsetup Rstrobe w Margin Requirements Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Recommended Margins Nand Flash Read Timing Requirements Meeting AC Timing Requirements for Nand FlashEmif Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Nand Flash Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MEmif Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Parameter Setting Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Nand Flash mode for chip select External Memory Interface Emif Registers Offset Acronym Register Description Bit Field Value Description Revision Code and Status Register RcsrRevision Code and Status Register Rcsr Field Descriptions CS5WAIT CS4WAIT CS3WAIT CS2WAIT Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 WP3 EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 WR2 WR1 WR0 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3 WRM3 WRM2 WRM1 WRM0 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3 AT bit in the Emif interrupt raw register Eirr WRMSET3 WRMSET2 WRMSET1 WRMSET0 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3 Bit in Eimcr WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3 Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Status Register Nandfsr Field Descriptions Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Waitst P8E P4E P2E P1E Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8O Document Revision History Additions/Modifications/Deletions Rfid Products ApplicationsDSP