Manuals / Brands / Computer Equipment / Computer Hardware / Texas Instruments / Computer Equipment / Computer Hardware

Texas Instruments TMS320DM646X DMSOC Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued)

1 64

Download 64 pages, 408.81 Kb

www.ti.com

Registers

Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued)

Bit Field Value Description

0 ATM Asynchronous Timeout Masked. This bit is set to 1 by hardware to indicate that during an extended

asynchronous memory access cycle the EM_WAITnpin did not go inactive within the number of cycles

defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR), provided

that the ATMSET bit is set to 1 in the EMIF interrupt mask set register (EIMSR).

0 Indicates that an asynchronous timeout interrupt has not been generated. Writing a 0 has no effect.

1 Indicates that an asynchronous timeout interrupt has been generated. Writing a 1 will clear this bit and

the AT bit in the EMIF interrupt raw register (EIRR).

SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)

Submit Documentation Feedback

Contents

Main Page Page Page Page Preface Read This First About This Manual Notational Conventions Related Documentation From Texas Instruments Page User's Guide Asynchronous External Memory Interface (EMIF) 1 Introduction 1.1 Purpose of the Peripheral 1.2 Features 1.3 Functional Block Diagram 2 Architecture 2.1 Clock Control 2.2 EMIF Requests 2.3 Signal Descriptions 2.4 Pin Multiplexing 2.5 Asynchronous Controller and Interface Page Page Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued) Table 4. Description of the Asynchronous Wait Cycle Configuration Register (AWCCR) Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR) Table 6. Description of the EMIF Interrupt Mast Clear Register (EIMCR) Page Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high. Table 8. Asynchronous Write Operation in Normal Mode Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Page Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high. Table 10. Asynchronous Write Operation in Select Strobe Mode Figure 7. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode Page Page Page Page Page Page Page Page 3 Use Cases 3.1 Interfacing to Asynchronous SRAM (ASRAM) Page Figure 12. Timing Waveform of an ASRAM Read Page Page Figure 14. Timing Waveform of an ASRAM Read with PCB Delays W_STROBE wtWP(m) tcyc *1 W_SETUP )W_STROBE wmaxtEM_A )tAW(m) *tEM_WE t cyc , t EM_D ) t DS (m) * t tcyc *1 W_HOLD wmaxtEM_WE )tWR(m) *tEM_A t cyc , t EM_WE ) t DH (m) * t tcyc *1 W_SETUP )W_STROBE )W_HOLD wtWC(m) tcyc *3 Figure 15. Timing Waveform of an ASRAM Write with PCB Delays Page Page 3.2 Interfacing to NAND Flash Page Page Page Figure 17. Timing Waveform of a NAND Flash Command Write Figure 18. Timing Waveform of a NAND Flash Address Write Figure 19. Timing Waveform of a NAND Flash Data Write Use Cases Table 29. NAND Flash Timing Requirements for HY27UA081G1M Example Page Page 4 Registers Table 32. External Memory Interface (EMIF) Registers 4.1 Revision Code and Status Register (RCSR) Table 33. Revision Code and Status Register (RCSR) Field Descriptions 4.2 Asynchronous Wait Cycle Configuration Register (AWCCR) Figure 21. Asynchronous Wait Cycle Configuration Register (AWCCR) Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued) 4.3 Asynchronous n Configuration Registers (A1CR-A4CR) Table 35. Asynchronous nConfiguration Register (ACFGn) Field Descriptions 4.4 EMIF Interrupt Raw Register (EIRR) Table 36. EMIF Interrupt Raw Register (EIRR) Field Descriptions 4.5 EMIF Interrupt Mask Register (EIMR) Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued) 4.6 EMIF Interrupt Mask Set Register (EIMSR) Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued) 4.7 EMIF Interrupt Mask Clear Register (EIMCR) Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued) 4.8 NAND Flash Control Register (NANDFCR) Table 40. NAND Flash Control Register (NANDFCR) Field Descriptions 4.9 NAND Flash Status Register (NANDFSR) 4.10 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) Figure 29. NAND Flash nECC Register (NANDECCn) Table 42. NAND Flash nECC Register (NANDECCn) Field Descriptions Appendix A Revision History IMPORTANT NOTICE